Dual-metal gate and gate–drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET).The effects of gate work function and gate–drain underlap leng...Dual-metal gate and gate–drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET).The effects of gate work function and gate–drain underlap length on the DC characteristics and analog/RF performance of CSP-TFET devices,such as the on-state current(I_(on)),ambipolar current(I_(amb)),transconductance(g_(m)),cut-off frequency(f_(T))and gain–bandwidth product(GBP),are analyzed and compared in this work.Also,a combination of both the dual-metal gate and gate–drain underlap designs has been proposed for the C-shaped pocket dual metal underlap TFET(CSP-DMUN-TFET),which contains a C-shaped pocket area that significantly increases the on-state current of the device;this combination design substantially reduces the ambipolar current.The results show that the CSP-DMUN-TFET demonstrates an excellent performance,including high I_(on)(9.03×10^(-4)A/μm),high I_(on)/I_(off)(~10^(11)),low SS_(avg)(~13 mV/dec),and low I_(amb)(2.15×10^(-17)A/μm).The CSP-DMUN-TFET has the capability to fully suppress ambipolar currents while maintaining high on-state currents,making it a potential replacement in the next generation of semiconductor devices.展开更多
We investigate the performance of an 18 nm gate length AIInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0.83In0.17N and narrowband G...We investigate the performance of an 18 nm gate length AIInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0.83In0.17N and narrowband GaN layers, along with high-k Al2O3 as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas （2DEG） density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering （DIBL）, subthreshold slope （SS）, delay, threshold voltage （Vt）, Ion/Ioff ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, Ion, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize theIoff and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.展开更多
Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short c...Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects （SCEs）, leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SO1 FinFET is one of the best multigate structures that has gained importance in all electronic design automation （EDA） industries due to its improved short channel effects （SCEs）, because of its more effective gate-controlling capabilities. In this paper, our aim is to ex- plore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evalu- ated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope （SS）, ON current （Ion）, OFF current （/off） and Ion/loll ratio. The potential benefits of SOl FinFET at drain-to-source voltage, liDS = 0.05 V and VDS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain （Av）, output conductance （go）, trans-conductance （gin）, gate capacitance （Cgg）, and cut-off frequency OCT = gm/2πCgg） with spacer region variations.展开更多
We propose an analytical model for drain current and inversion charge in the subthreshold region for an underlap DG FinFET by using the minimum channel potential method, i.e., the virtual source. The flicker and therm...We propose an analytical model for drain current and inversion charge in the subthreshold region for an underlap DG FinFET by using the minimum channel potential method, i.e., the virtual source. The flicker and thermal noise spectral density models are also developed using these charge and current models expression. The model is validated with already published experimental results of flicker noise for DG FinFETs. For an ultrathin body, the degradation of effective mobility and variation of the scattering parameter are considered. The effect of device parameters like gate length Lg and underlap length Lun on both flicker and thermal noise spectral densities are also analyzed. Increasing Lg and Lun, increases the effective gate length, which reduces drain current, resulting in decreased flicker and thermal noise density. A decrease of flicker noise is observed for an increase of frequency, which indicates that the device can be used for wide range of frequency applications.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.52177185 and 62174055)。
文摘Dual-metal gate and gate–drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET).The effects of gate work function and gate–drain underlap length on the DC characteristics and analog/RF performance of CSP-TFET devices,such as the on-state current(I_(on)),ambipolar current(I_(amb)),transconductance(g_(m)),cut-off frequency(f_(T))and gain–bandwidth product(GBP),are analyzed and compared in this work.Also,a combination of both the dual-metal gate and gate–drain underlap designs has been proposed for the C-shaped pocket dual metal underlap TFET(CSP-DMUN-TFET),which contains a C-shaped pocket area that significantly increases the on-state current of the device;this combination design substantially reduces the ambipolar current.The results show that the CSP-DMUN-TFET demonstrates an excellent performance,including high I_(on)(9.03×10^(-4)A/μm),high I_(on)/I_(off)(~10^(11)),low SS_(avg)(~13 mV/dec),and low I_(amb)(2.15×10^(-17)A/μm).The CSP-DMUN-TFET has the capability to fully suppress ambipolar currents while maintaining high on-state currents,making it a potential replacement in the next generation of semiconductor devices.
文摘We investigate the performance of an 18 nm gate length AIInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0.83In0.17N and narrowband GaN layers, along with high-k Al2O3 as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas （2DEG） density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering （DIBL）, subthreshold slope （SS）, delay, threshold voltage （Vt）, Ion/Ioff ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, Ion, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize theIoff and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.
文摘Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects （SCEs）, leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SO1 FinFET is one of the best multigate structures that has gained importance in all electronic design automation （EDA） industries due to its improved short channel effects （SCEs）, because of its more effective gate-controlling capabilities. In this paper, our aim is to ex- plore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evalu- ated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope （SS）, ON current （Ion）, OFF current （/off） and Ion/loll ratio. The potential benefits of SOl FinFET at drain-to-source voltage, liDS = 0.05 V and VDS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain （Av）, output conductance （go）, trans-conductance （gin）, gate capacitance （Cgg）, and cut-off frequency OCT = gm/2πCgg） with spacer region variations.
文摘We propose an analytical model for drain current and inversion charge in the subthreshold region for an underlap DG FinFET by using the minimum channel potential method, i.e., the virtual source. The flicker and thermal noise spectral density models are also developed using these charge and current models expression. The model is validated with already published experimental results of flicker noise for DG FinFETs. For an ultrathin body, the degradation of effective mobility and variation of the scattering parameter are considered. The effect of device parameters like gate length Lg and underlap length Lun on both flicker and thermal noise spectral densities are also analyzed. Increasing Lg and Lun, increases the effective gate length, which reduces drain current, resulting in decreased flicker and thermal noise density. A decrease of flicker noise is observed for an increase of frequency, which indicates that the device can be used for wide range of frequency applications.
基金supported by National Natural Science Foundation of China (No.51175362,No.51205271)Specialized Research Fund for the Doctoral Program of Higher Education (No.20121402120002)
