通用串行接口(Universal Serial Bus,USB)总线在实际应用中较为广泛,涉及各行业的电子设备,目前大部分为USB3.0设备。USB3.0总线传输速率高,信号链路插损、回损较大,导致USB设备连接存在不稳定问题,基于此,本文开展USB3.0总线链路的研...通用串行接口(Universal Serial Bus,USB)总线在实际应用中较为广泛,涉及各行业的电子设备,目前大部分为USB3.0设备。USB3.0总线传输速率高,信号链路插损、回损较大,导致USB设备连接存在不稳定问题,基于此,本文开展USB3.0总线链路的研究。本文以实际工程项目为基础,通过建立USB3.0完整布线链路仿真模型,对影响线路链路不同影响因素进行仿真对比分析,综合仿真对比结果及实际布局布线情况,提出USB3.0布线链路的优化策略,最终仿真完整布线链路插损、回损结果能够满足USB3.0协议规范要求且留有一定余量,对实际产品USB3.0布线链路优化具有很强的指导意义。展开更多
To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were iden...To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board （PCB） side, split between redistribution layer （RDL） and Cu under bump metallization （UBM）, RDL fracture, bulk cracks and partial bulk and intermetallic compound （IMC） cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.展开更多
文摘通用串行接口(Universal Serial Bus,USB)总线在实际应用中较为广泛,涉及各行业的电子设备,目前大部分为USB3.0设备。USB3.0总线传输速率高,信号链路插损、回损较大,导致USB设备连接存在不稳定问题,基于此,本文开展USB3.0总线链路的研究。本文以实际工程项目为基础,通过建立USB3.0完整布线链路仿真模型,对影响线路链路不同影响因素进行仿真对比分析,综合仿真对比结果及实际布局布线情况,提出USB3.0布线链路的优化策略,最终仿真完整布线链路插损、回损结果能够满足USB3.0协议规范要求且留有一定余量,对实际产品USB3.0布线链路优化具有很强的指导意义。
基金Projects(51475072,51171036)supported by the National Natural Science Foundation of China
文摘To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board （PCB） side, split between redistribution layer （RDL） and Cu under bump metallization （UBM）, RDL fracture, bulk cracks and partial bulk and intermetallic compound （IMC） cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.
