This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is go...This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.展开更多
Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performanc...Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.展开更多
This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack chan...This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.展开更多
This paper quantitatively discusses the influence of well contact on single-event transient(SET)in sub-20 nm FinFET by two-photon absorption(TPA)pulse laser.Two groups of inverter chains were designed to investigate t...This paper quantitatively discusses the influence of well contact on single-event transient(SET)in sub-20 nm FinFET by two-photon absorption(TPA)pulse laser.Two groups of inverter chains were designed to investigate the impact of well contact distance on the FinFET process.The experimental results show that the SET pulse width has a bimodal symmetric distribution,which is different from that of a bulk planar CMOS device.To investigate the detailed mechanism of the phenomenon,a high-precision FinFET TCAD model was established,in which both Id-Vd and Id-Vg errors were less than 10%compared to the SPICE model provided by the commercial process.TCAD simulation under heavy ion injection showed the mechanism of the abnormal phenomenon,where the well contact plays a major role in charge collection at the near-well contact distance,while the source plays a major role at the far distance.This phenomenon is completely different from that of planar CMOS devices.This indicates that the SET mechanism becomes more complicated during the FinFET process.Therefore,more effective SET hardening methods should be investigated for FinFET.展开更多
The strain impact on hole mobility in the GOI tri-gate pFETs is investigated by simulating the strained Ge with quantum confinement from band structure to electro-static distribution as well as the effective mobility....The strain impact on hole mobility in the GOI tri-gate pFETs is investigated by simulating the strained Ge with quantum confinement from band structure to electro-static distribution as well as the effective mobility. Lattice mismatch strain induced by HfO2 warps and reshapes the valence subbands, and reduces the hole effective masses. The maximum value of hole density is observed near the top comers of the channel. The hole density is decreased by the lattice mismatch strain. The phonon scattering rate is degraded by strain, which results in higher hole mobility.展开更多
A CMOS FinFET fabricated on bulk silicon substrate is demonstrated.Besides owning a FinFET structure similar to the original FinFET on SOI,the device combines a grooved planar MOSFET in the Si substrate and the fabric...A CMOS FinFET fabricated on bulk silicon substrate is demonstrated.Besides owning a FinFET structure similar to the original FinFET on SOI,the device combines a grooved planar MOSFET in the Si substrate and the fabrication processes are fully compatible with conventional CMOS process,including salicide technology.The CMOS device,inverter,and CMOS ring oscillator of this structure with normal poly silicon and W/TiN gate electrode are fabricated respectively.Driving current and sub threshold characteristics of CMOS FinFET on Si substrate with actual gate length of 110nm are studied.The inverter operates correctly and minimum per stage delay of 201 stage ring oscillator is 146ps at V d=3V.The result indicates the device is a promising candidate for the application of future VLSI circuit.展开更多
An SOI MOSFET with FINFET structure is simulated using a 3 D simulator. I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully investigated.SCE can be well c...An SOI MOSFET with FINFET structure is simulated using a 3 D simulator. I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully investigated.SCE can be well controlled by reducing fin height.Good performance can be achieved with thin height,so fin height is considered as a key parameter in device design.Simulation results show that FINFETs present performance superior to conventional single gate devices.展开更多
文摘This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.
文摘Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.
文摘This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.
基金supported by Natural Science Foundation of China(Nos.62174180 and 62304258)National Key R&D Program of China(No.2023YFA1609000)。
文摘This paper quantitatively discusses the influence of well contact on single-event transient(SET)in sub-20 nm FinFET by two-photon absorption(TPA)pulse laser.Two groups of inverter chains were designed to investigate the impact of well contact distance on the FinFET process.The experimental results show that the SET pulse width has a bimodal symmetric distribution,which is different from that of a bulk planar CMOS device.To investigate the detailed mechanism of the phenomenon,a high-precision FinFET TCAD model was established,in which both Id-Vd and Id-Vg errors were less than 10%compared to the SPICE model provided by the commercial process.TCAD simulation under heavy ion injection showed the mechanism of the abnormal phenomenon,where the well contact plays a major role in charge collection at the near-well contact distance,while the source plays a major role at the far distance.This phenomenon is completely different from that of planar CMOS devices.This indicates that the SET mechanism becomes more complicated during the FinFET process.Therefore,more effective SET hardening methods should be investigated for FinFET.
文摘The strain impact on hole mobility in the GOI tri-gate pFETs is investigated by simulating the strained Ge with quantum confinement from band structure to electro-static distribution as well as the effective mobility. Lattice mismatch strain induced by HfO2 warps and reshapes the valence subbands, and reduces the hole effective masses. The maximum value of hole density is observed near the top comers of the channel. The hole density is decreased by the lattice mismatch strain. The phonon scattering rate is degraded by strain, which results in higher hole mobility.
文摘A CMOS FinFET fabricated on bulk silicon substrate is demonstrated.Besides owning a FinFET structure similar to the original FinFET on SOI,the device combines a grooved planar MOSFET in the Si substrate and the fabrication processes are fully compatible with conventional CMOS process,including salicide technology.The CMOS device,inverter,and CMOS ring oscillator of this structure with normal poly silicon and W/TiN gate electrode are fabricated respectively.Driving current and sub threshold characteristics of CMOS FinFET on Si substrate with actual gate length of 110nm are studied.The inverter operates correctly and minimum per stage delay of 201 stage ring oscillator is 146ps at V d=3V.The result indicates the device is a promising candidate for the application of future VLSI circuit.
文摘An SOI MOSFET with FINFET structure is simulated using a 3 D simulator. I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully investigated.SCE can be well controlled by reducing fin height.Good performance can be achieved with thin height,so fin height is considered as a key parameter in device design.Simulation results show that FINFETs present performance superior to conventional single gate devices.
