A track/hold （T/H） circuit of broad bandwidth high speed pipeline structure ADC based on the super frequency application is designed in the paper. Some main factors affecting SNR of high speed ADC, such as aperture ...A track/hold （T/H） circuit of broad bandwidth high speed pipeline structure ADC based on the super frequency application is designed in the paper. Some main factors affecting SNR of high speed ADC, such as aperture uncertainty, switch capacitor, and MOS switch, are analyzed. In the circuit, the full-differential structure and the bottom plate sampling technique are adopted to optimize the switch capacitors and MOS switches. The result based on the Spectre simulation on 0.35pm Bi- CMOS technology indicate that the aperture uncertainty, charge-injection, and non-linearity of clock feed-through are considerably restrained and the performance of T/H circuit is enhanced展开更多
Design of a high performance track and hold （T/H） circuit for high-resolution high-speed analog-to-digital converter （ADC） is presented, which has been implemented in 0.18 μm CMOS process. An improved bootstrappe...Design of a high performance track and hold （T/H） circuit for high-resolution high-speed analog-to-digital converter （ADC） is presented, which has been implemented in 0.18 μm CMOS process. An improved bootstrapped and bulk-switching technique is introduced to greatly minimize the nonlinearity of sampling network over a wide bandwidth, and the addition of a modified pre-charge circuit helps reducing the total power consumption. The experimental results show that the proposed T/H circuit achieves over 77 dB SFDR （spurious-free dynamic range） and 70 dB THD （total harmonic distortion） at 100 MHz sampling rate and maintains the performance with input frequency up to 305 MHz while consuming 47 mW power.展开更多
The multi-tone frequency modulation （FM） signal transferred through track circuit in automatic train control （ATC） system is analyzed. A digital filter with ideal sloping shape in frequency domain is designed for ...The multi-tone frequency modulation （FM） signal transferred through track circuit in automatic train control （ATC） system is analyzed. A digital filter with ideal sloping shape in frequency domain is designed for frequency discrimination. With this filter, the FM signal is converted into AM-FM signal by frequency-to-amplitude conversion. The modulating signal is finally extracted from the envelope of the AM-FM signal. Simulations show that the digital demodulation method could accurately recover the modulating signal in low signal noise ratio （SNR） circumstance, and has good performance in suppressing interference of harmonies of traction current frequency. The feasibility of the proposed method is proved in a hardware system based on SHARC DSP.展开更多
Evaluation of the health state and prediction of the remaining life of the track circuit are important for the safe operation of the equipment of railway signal system.Based on support vector data description(SVDD)and...Evaluation of the health state and prediction of the remaining life of the track circuit are important for the safe operation of the equipment of railway signal system.Based on support vector data description(SVDD)and gray prediction,this paper illustrates a method of life prediction for ZPW-2000A track circuit,which combines entropy weight method,SVDD,Mahalanobis distance and negative conversion function to set up a health state assessment model.The model transforms multiple factors affecting the health state into a health index named H to reflect the health state of the equipment.According to H,the life prediction model of ZPW-2000A track circuit equipment is established by means of gray prediction so as to predict the trend of health state of the equipment.The certification of the example shows that the method can visually reflect the health state and effectively predict the remaining life of the equipment.It also provides a theoretical basis to further improve the maintenance and management for ZPW-2000A track circuit.展开更多
At present,ZPW-2000 track circuit fault diagnosis is artificially analyzed and monitored.Its discrimination method not only is low efficient and takes a long period,but also requires highly experienced personnel to an...At present,ZPW-2000 track circuit fault diagnosis is artificially analyzed and monitored.Its discrimination method not only is low efficient and takes a long period,but also requires highly experienced personnel to analyze the data.Therefore,we introduce kernel principal component analysis and stacked auto-encoder network(KPCA-SAD)into the fault diagnosis of ZPW-2000 track circuit.According to the working principle and fault characteristics of track circuit,a fault diagnosis model of KPCA-SAE network is established.The relevant parameters of key components recorded in the data collected by field staff are used as the fault feature parameters.The KPCA method is used to reduce the dimension and noise of fault document matrix to avoid information redundancy.The SAE network is trained by the processed fault data.The model parameters are optimized overall by using back propagation(BP)algorithm.The KPCA-SAE model is simulated in Matlab platform and is finally proved to be effective and feasible.Compared with the traditional method of artificially analyzing fault data and other intelligent algorithms,the KPCA-SAE based classifier has higher fault identification accuracy.展开更多
Tow different computer calculation methods for distortion of the wide-band diode bridge track and hold amplifier (THA) are presented based on a high frequency Schottky diode model. One of the computer programs calcula...Tow different computer calculation methods for distortion of the wide-band diode bridge track and hold amplifier (THA) are presented based on a high frequency Schottky diode model. One of the computer programs calculates the distortion of weekly nonlinear THA based on the KCL and the nonlinear-current method. The other calculates the weekly nonlinear distortion by using a Volterra series method and a nodal formulation. Comparative calculation results for the diode bridge THA have shown good agreement with these two computer program calculation methods, whereas the overall computational efficiency of the nonlinear-current method is better than that of the nodal formulation method in a special evaluation.展开更多
With research on the carrier phase synchronization and symbol synchronization algorithm of demodulation module, a synchronization circuit system is designed for GPS software receiver based on field programmable gate a...With research on the carrier phase synchronization and symbol synchronization algorithm of demodulation module, a synchronization circuit system is designed for GPS software receiver based on field programmable gate array （FPGA）, and a series of experiment is done on the hardware platform. The result shows the all-digital synchronization and demodulation of GPS intermediate frequency （IF） signal can be realized and applied in embedded real-time GPS software receiver system. It is verified that the decision-directed joint tracking algorithm of carrier phase and symbol timing for received signals from GPS is reasonable. In addition, the loop works steadily and can be used for receiving GPS signals using synchronous demodulation. The synchronization circuit for GPS software receiver designed based on FPGA has the features of low cost, miniaturization, low power and real-time. Surely, it will become one of the development directions for GPS and even GNSS embedded real-time software receiver.展开更多
We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinationa...We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (TEMs) of the circuit. We propose a class of acyclic sequential circuits for which the number of maximal TEMs is one, i.e, the maximum TEM exists. For a circuit in the class, test generation can be performed by using only the maximum TEM. The proposed class of sequential circuits with the maximum TEM properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can be also performed by using a combinational test generator. Therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.展开更多
文摘A track/hold （T/H） circuit of broad bandwidth high speed pipeline structure ADC based on the super frequency application is designed in the paper. Some main factors affecting SNR of high speed ADC, such as aperture uncertainty, switch capacitor, and MOS switch, are analyzed. In the circuit, the full-differential structure and the bottom plate sampling technique are adopted to optimize the switch capacitors and MOS switches. The result based on the Spectre simulation on 0.35pm Bi- CMOS technology indicate that the aperture uncertainty, charge-injection, and non-linearity of clock feed-through are considerably restrained and the performance of T/H circuit is enhanced
文摘Design of a high performance track and hold （T/H） circuit for high-resolution high-speed analog-to-digital converter （ADC） is presented, which has been implemented in 0.18 μm CMOS process. An improved bootstrapped and bulk-switching technique is introduced to greatly minimize the nonlinearity of sampling network over a wide bandwidth, and the addition of a modified pre-charge circuit helps reducing the total power consumption. The experimental results show that the proposed T/H circuit achieves over 77 dB SFDR （spurious-free dynamic range） and 70 dB THD （total harmonic distortion） at 100 MHz sampling rate and maintains the performance with input frequency up to 305 MHz while consuming 47 mW power.
文摘The multi-tone frequency modulation （FM） signal transferred through track circuit in automatic train control （ATC） system is analyzed. A digital filter with ideal sloping shape in frequency domain is designed for frequency discrimination. With this filter, the FM signal is converted into AM-FM signal by frequency-to-amplitude conversion. The modulating signal is finally extracted from the envelope of the AM-FM signal. Simulations show that the digital demodulation method could accurately recover the modulating signal in low signal noise ratio （SNR） circumstance, and has good performance in suppressing interference of harmonies of traction current frequency. The feasibility of the proposed method is proved in a hardware system based on SHARC DSP.
基金Natural Science Fund of Gansu Province(No.1310RJZA046)
文摘Evaluation of the health state and prediction of the remaining life of the track circuit are important for the safe operation of the equipment of railway signal system.Based on support vector data description(SVDD)and gray prediction,this paper illustrates a method of life prediction for ZPW-2000A track circuit,which combines entropy weight method,SVDD,Mahalanobis distance and negative conversion function to set up a health state assessment model.The model transforms multiple factors affecting the health state into a health index named H to reflect the health state of the equipment.According to H,the life prediction model of ZPW-2000A track circuit equipment is established by means of gray prediction so as to predict the trend of health state of the equipment.The certification of the example shows that the method can visually reflect the health state and effectively predict the remaining life of the equipment.It also provides a theoretical basis to further improve the maintenance and management for ZPW-2000A track circuit.
基金National Natural Science Foundation of China(No.61763023)。
文摘At present,ZPW-2000 track circuit fault diagnosis is artificially analyzed and monitored.Its discrimination method not only is low efficient and takes a long period,but also requires highly experienced personnel to analyze the data.Therefore,we introduce kernel principal component analysis and stacked auto-encoder network(KPCA-SAD)into the fault diagnosis of ZPW-2000 track circuit.According to the working principle and fault characteristics of track circuit,a fault diagnosis model of KPCA-SAE network is established.The relevant parameters of key components recorded in the data collected by field staff are used as the fault feature parameters.The KPCA method is used to reduce the dimension and noise of fault document matrix to avoid information redundancy.The SAE network is trained by the processed fault data.The model parameters are optimized overall by using back propagation(BP)algorithm.The KPCA-SAE model is simulated in Matlab platform and is finally proved to be effective and feasible.Compared with the traditional method of artificially analyzing fault data and other intelligent algorithms,the KPCA-SAE based classifier has higher fault identification accuracy.
文摘Tow different computer calculation methods for distortion of the wide-band diode bridge track and hold amplifier (THA) are presented based on a high frequency Schottky diode model. One of the computer programs calculates the distortion of weekly nonlinear THA based on the KCL and the nonlinear-current method. The other calculates the weekly nonlinear distortion by using a Volterra series method and a nodal formulation. Comparative calculation results for the diode bridge THA have shown good agreement with these two computer program calculation methods, whereas the overall computational efficiency of the nonlinear-current method is better than that of the nodal formulation method in a special evaluation.
基金supported in part by the National High Technology Research and Development Program of China (863 Program)(2006AA12A108)CSC International Scholarship (2008104769)
文摘With research on the carrier phase synchronization and symbol synchronization algorithm of demodulation module, a synchronization circuit system is designed for GPS software receiver based on field programmable gate array （FPGA）, and a series of experiment is done on the hardware platform. The result shows the all-digital synchronization and demodulation of GPS intermediate frequency （IF） signal can be realized and applied in embedded real-time GPS software receiver system. It is verified that the decision-directed joint tracking algorithm of carrier phase and symbol timing for received signals from GPS is reasonable. In addition, the loop works steadily and can be used for receiving GPS signals using synchronous demodulation. The synchronization circuit for GPS software receiver designed based on FPGA has the features of low cost, miniaturization, low power and real-time. Surely, it will become one of the development directions for GPS and even GNSS embedded real-time software receiver.
文摘We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (TEMs) of the circuit. We propose a class of acyclic sequential circuits for which the number of maximal TEMs is one, i.e, the maximum TEM exists. For a circuit in the class, test generation can be performed by using only the maximum TEM. The proposed class of sequential circuits with the maximum TEM properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can be also performed by using a combinational test generator. Therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.
