The efficient implementation of the Advanced Encryption Standard(AES)is crucial for network data security.This paper presents novel hardware implementations of the AES S-box,a core component,using tower field represen...The efficient implementation of the Advanced Encryption Standard(AES)is crucial for network data security.This paper presents novel hardware implementations of the AES S-box,a core component,using tower field representations and Boolean Satisfiability(SAT)solvers.Our research makes several significant contri-butions to the field.Firstly,we have optimized the GF(24)inversion,achieving a remarkable 31.35%area reduction(15.33 GE)compared to the best known implementations.Secondly,we have enhanced multiplication implementa-tions for transformation matrices using a SAT-method based on local solutions.This approach has yielded notable improvements,such as a 22.22%reduction in area(42.00 GE)for the top transformation matrix in GF((24)2)-type S-box implementation.Furthermore,we have proposed new implementations of GF(((22)2)2)-type and GF((24)2)-type S-boxes,with the GF(((22)2)2)-type demonstrating superior performance.This implementation offers two variants:a small area variant that sets new area records,and a fast variant that establishes new benchmarks in Area-Execution-Time(AET)and energy consumption.Our approach significantly improves upon existing S-box implementations,offering advancements in area,speed,and energy consumption.These optimizations contribute to more efficient and secure AES implementations,potentially enhancing various cryptographic applications in the field of network security.展开更多
The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization...The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.展开更多
Let p be a prime and K be a number field with non-trivial p-class group ClpK. A crucial step in identifying the Galois group G∞p of the maximal unramified pro-p extension of K is to determine its two-stage approximat...Let p be a prime and K be a number field with non-trivial p-class group ClpK. A crucial step in identifying the Galois group G∞p of the maximal unramified pro-p extension of K is to determine its two-stage approximation M=G2pk, that is the second derived quotient M≃G/Gn. The family τ1K of abelian type invariants of the p-class groups ClpL of all unramified cyclic extensions L/K of degree p is called the index- abelianization data (IPAD) of K. It is able to specify a finite batch of contestants for the second p-class group M of K. In this paper we introduce two different kinds of generalized IPADs for obtaining more sophisticated results. The multi-layered IPAD (τ1Kτ(2)K) includes data on unramified abelian extensions L/K of degree p2 and enables sharper bounds for the order of M in the case Clpk≃(p,p,p), where current im-plementations of the p-group generation algorithm fail to produce explicit contestants for M , due to memory limitations. The iterated IPAD of second order τ(2)K contains information on non-abelian unramified extensions L/K of degree p2, or even p3, and admits the identification of the p-class tower group G for various infinite series of quadratic fields K=Q(√d) with ClpK≃(p,p) possessing a p-class field tower of exact length lpK=3 as a striking novelty.展开更多
基金supported in part by the National Natural Science Foundation of China(No.62162016)in part by the Innovation Project of Guangxi Graduate Education(Nos.YCBZ2023132 and YCSW2023304).
文摘The efficient implementation of the Advanced Encryption Standard(AES)is crucial for network data security.This paper presents novel hardware implementations of the AES S-box,a core component,using tower field representations and Boolean Satisfiability(SAT)solvers.Our research makes several significant contri-butions to the field.Firstly,we have optimized the GF(24)inversion,achieving a remarkable 31.35%area reduction(15.33 GE)compared to the best known implementations.Secondly,we have enhanced multiplication implementa-tions for transformation matrices using a SAT-method based on local solutions.This approach has yielded notable improvements,such as a 22.22%reduction in area(42.00 GE)for the top transformation matrix in GF((24)2)-type S-box implementation.Furthermore,we have proposed new implementations of GF(((22)2)2)-type and GF((24)2)-type S-boxes,with the GF(((22)2)2)-type demonstrating superior performance.This implementation offers two variants:a small area variant that sets new area records,and a fast variant that establishes new benchmarks in Area-Execution-Time(AET)and energy consumption.Our approach significantly improves upon existing S-box implementations,offering advancements in area,speed,and energy consumption.These optimizations contribute to more efficient and secure AES implementations,potentially enhancing various cryptographic applications in the field of network security.
文摘The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.
文摘Let p be a prime and K be a number field with non-trivial p-class group ClpK. A crucial step in identifying the Galois group G∞p of the maximal unramified pro-p extension of K is to determine its two-stage approximation M=G2pk, that is the second derived quotient M≃G/Gn. The family τ1K of abelian type invariants of the p-class groups ClpL of all unramified cyclic extensions L/K of degree p is called the index- abelianization data (IPAD) of K. It is able to specify a finite batch of contestants for the second p-class group M of K. In this paper we introduce two different kinds of generalized IPADs for obtaining more sophisticated results. The multi-layered IPAD (τ1Kτ(2)K) includes data on unramified abelian extensions L/K of degree p2 and enables sharper bounds for the order of M in the case Clpk≃(p,p,p), where current im-plementations of the p-group generation algorithm fail to produce explicit contestants for M , due to memory limitations. The iterated IPAD of second order τ(2)K contains information on non-abelian unramified extensions L/K of degree p2, or even p3, and admits the identification of the p-class tower group G for various infinite series of quadratic fields K=Q(√d) with ClpK≃(p,p) possessing a p-class field tower of exact length lpK=3 as a striking novelty.
