High spectral efficiency is essential in design of multimedia communication systems such as L-band mobile in addition to various requirements of transmission quality. Time-interleaved A/D converter （TI-ADC） is an ef...High spectral efficiency is essential in design of multimedia communication systems such as L-band mobile in addition to various requirements of transmission quality. Time-interleaved A/D converter （TI-ADC） is an effective candidate to implement wide-band ADC with relatively slow circuits accounting for digital spectrum management. However, practical performance of TI-ADC is largely limited because of mismatches between different channels originated from manufacturing process variations. In this paper, a blind adaptive method is proposed to correct gain mismatch errors in TI-ADC, and it is verified through simulations on a two-channel TI-ADC. In proposed method, gain mismatch error is estimated and corrected in an adaptive scheme. Proposed compensated T1-ADC architecture is structurally very simple and hence suitable for realiza- tion in integrated circuits. Besides, proposed digital compensation algorithm not only is computationally efficient but also provides an improvement of 32.7 dB in the performance of two-channel TI ADC.展开更多
A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels ...A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.展开更多
This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the...This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.展开更多
A capacitor self-calibration circuit used in a successive approximation analog-to-digital converter （SA-ADC） is presented. This capacitor self-calibration circuit can calibrate erroneous data and work with the ADC b...A capacitor self-calibration circuit used in a successive approximation analog-to-digital converter （SA-ADC） is presented. This capacitor self-calibration circuit can calibrate erroneous data and work with the ADC by adding an additional clock period. This circuit is used in a 10 bit 32 Msample/s time-interleaved SA- ADC. The chip is implemented with Chart 0. 25 μm 2. 5 V process and totally occupies an area of 1.4 mm× 1.3 mm. After calibration, the simulated signal-to-noise ratio （SNR） is 59. 586 1 dB and the spurious-free dynamic range （SFDR） is 70. 246 dB at 32 MHz. The measured signal-to-noise and distortion ratio （SINAD） is 44. 82 dB and the SFDR is 63. 760 4 dB when the ADC samples a 5.8 MHz sinusoid wave.展开更多
为解决传统电平交叉模数转换器(LC ADC)精度较低和噪声整形逐次逼近寄存器(NS SAR)ADC功耗较大的问题,提出了一种应用于移动物联网(IoT)随机稀疏信号采集的LC-NS SAR ADC。在NS SAR ADC前端插入8 bit的LC ADC作为输入信号活跃度的预检...为解决传统电平交叉模数转换器(LC ADC)精度较低和噪声整形逐次逼近寄存器(NS SAR)ADC功耗较大的问题,提出了一种应用于移动物联网(IoT)随机稀疏信号采集的LC-NS SAR ADC。在NS SAR ADC前端插入8 bit的LC ADC作为输入信号活跃度的预检测电路,在电平交叉发生后开启NS SAR ADC的转换。二阶无源噪声整形电路积分过程只在事件触发后发生,从而能够根据输入信号的活跃度动态调节整体功耗。在1.8 V 180 nm CMOS工艺、采样率为40 kS/s、过采样率(OSR)为20、带宽为1 kHz下对该ADC进行仿真验证,结果表明信噪失真比(SNDR)达到87 dB,电路功耗为2.70μW,心电图信号输入时功耗仅为0.79μW,相较于传统等间隔奈奎斯特采样ADC,采样点减少了73%,在处理生物医学信号时实现了约5∶1的数据压缩比,Schreier品质因数(FoMs)和Walden品质因数(FoMw)分别为172.6 dB和67.0 fJ/conv.step。展开更多
Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is pro...Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper.The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals.The detected sample-time error is corrected by a voltage-controlled sampling switch.The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB,and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration.The calibration convergence time is about 20000 sampling intervals.展开更多
A high performance 10-bit 100-MS/s two-channel time-interleaved pipelined ADC is designed for intermediate frequency 3G receivers,and OTA is shared among the channels for low power dissipation.Offset mismatch, gain mi...A high performance 10-bit 100-MS/s two-channel time-interleaved pipelined ADC is designed for intermediate frequency 3G receivers,and OTA is shared among the channels for low power dissipation.Offset mismatch, gain mismatch and time skew mismatch are overcome by OTA sharing,increasing the accuracy of each channel and global passive sampling respectively.The linearity deterioration caused by the charge injection of the output switch and the crosstalk of the off-switch capacitor is removed by modifying the clock signal arrangement.The total power consumption of the presented ADC is 70 mW from a 3.3-V power supply.Fabricated in a 180-nm CMOS process,the core of the prototype occupies an area of 2.5×1.5 mm;,achieving more than 70-dB spurious-free dynamic range and over 56-dB signal-to-noise distortion ratio over the Nyquist input band at 100-MHz sampling frequency.展开更多
基金Iran’s Telecommunication Research Center(ITRC)(No.500/3653)
文摘High spectral efficiency is essential in design of multimedia communication systems such as L-band mobile in addition to various requirements of transmission quality. Time-interleaved A/D converter （TI-ADC） is an effective candidate to implement wide-band ADC with relatively slow circuits accounting for digital spectrum management. However, practical performance of TI-ADC is largely limited because of mismatches between different channels originated from manufacturing process variations. In this paper, a blind adaptive method is proposed to correct gain mismatch errors in TI-ADC, and it is verified through simulations on a two-channel TI-ADC. In proposed method, gain mismatch error is estimated and corrected in an adaptive scheme. Proposed compensated T1-ADC architecture is structurally very simple and hence suitable for realiza- tion in integrated circuits. Besides, proposed digital compensation algorithm not only is computationally efficient but also provides an improvement of 32.7 dB in the performance of two-channel TI ADC.
基金Supported by the National Natural Science Foundation of China (No. 61076026)
文摘A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.
文摘This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.
文摘A capacitor self-calibration circuit used in a successive approximation analog-to-digital converter （SA-ADC） is presented. This capacitor self-calibration circuit can calibrate erroneous data and work with the ADC by adding an additional clock period. This circuit is used in a 10 bit 32 Msample/s time-interleaved SA- ADC. The chip is implemented with Chart 0. 25 μm 2. 5 V process and totally occupies an area of 1.4 mm× 1.3 mm. After calibration, the simulated signal-to-noise ratio （SNR） is 59. 586 1 dB and the spurious-free dynamic range （SFDR） is 70. 246 dB at 32 MHz. The measured signal-to-noise and distortion ratio （SINAD） is 44. 82 dB and the SFDR is 63. 760 4 dB when the ADC samples a 5.8 MHz sinusoid wave.
文摘为解决传统电平交叉模数转换器(LC ADC)精度较低和噪声整形逐次逼近寄存器(NS SAR)ADC功耗较大的问题,提出了一种应用于移动物联网(IoT)随机稀疏信号采集的LC-NS SAR ADC。在NS SAR ADC前端插入8 bit的LC ADC作为输入信号活跃度的预检测电路,在电平交叉发生后开启NS SAR ADC的转换。二阶无源噪声整形电路积分过程只在事件触发后发生,从而能够根据输入信号的活跃度动态调节整体功耗。在1.8 V 180 nm CMOS工艺、采样率为40 kS/s、过采样率(OSR)为20、带宽为1 kHz下对该ADC进行仿真验证,结果表明信噪失真比(SNDR)达到87 dB,电路功耗为2.70μW,心电图信号输入时功耗仅为0.79μW,相较于传统等间隔奈奎斯特采样ADC,采样点减少了73%,在处理生物医学信号时实现了约5∶1的数据压缩比,Schreier品质因数(FoMs)和Walden品质因数(FoMw)分别为172.6 dB和67.0 fJ/conv.step。
基金supported by the National Natural Science Foundation of China(No.61006025)the Special Research Funds for Doctoral Program of Higher Education of China(No.20100071110026)
文摘Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper.The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals.The detected sample-time error is corrected by a voltage-controlled sampling switch.The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB,and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration.The calibration convergence time is about 20000 sampling intervals.
基金supported by the National Natural Science Foundation of China(No.90707002)
文摘A high performance 10-bit 100-MS/s two-channel time-interleaved pipelined ADC is designed for intermediate frequency 3G receivers,and OTA is shared among the channels for low power dissipation.Offset mismatch, gain mismatch and time skew mismatch are overcome by OTA sharing,increasing the accuracy of each channel and global passive sampling respectively.The linearity deterioration caused by the charge injection of the output switch and the crosstalk of the off-switch capacitor is removed by modifying the clock signal arrangement.The total power consumption of the presented ADC is 70 mW from a 3.3-V power supply.Fabricated in a 180-nm CMOS process,the core of the prototype occupies an area of 2.5×1.5 mm;,achieving more than 70-dB spurious-free dynamic range and over 56-dB signal-to-noise distortion ratio over the Nyquist input band at 100-MHz sampling frequency.
