Timing speculative(TS)architecture is promising for improving the energy efficiency of microprocessors.Error recovery units,designed for tolerating occasional timing errors,have been used to support a wider range of v...Timing speculative(TS)architecture is promising for improving the energy efficiency of microprocessors.Error recovery units,designed for tolerating occasional timing errors,have been used to support a wider range of voltage scaling,therefore to achieve a better energy efficiency.More specifically,the timing error rate,influenced mainly by data forwarding,is the bottleneck for voltage down-scaling in TS processors.In this paper,a new Timing Error Aware Register Allocation method is proposed.First,we designed the Dependency aware Interference Graph(DIG)construction to get the information of Read after Write(RAW)in programs.To build the construction,we get the disassemble code as input and suppose that there are unlimited registers,the same way as so-called virtual registers in many compilers.Then we change the disassemble codes to the SSA form for each basic block to make sure the registers are defined only once.Based on the DIG construction,registers were real-located to eliminate the timing error,by loosening the RAW dependencies.We con-struct the DIG for each function of the program and sort the edge of DIG by an increasing weight order.Since a smaller weighted-edge value means that its owner nodes have more frequent access in instruction flows,we expect it in different registers with no read-write dependency.At the same time,we make sure that there are no additional new spill codes emerging in our algorithm to minimize the rate of spill code.A high rate of spill code will not only decrease the performance of the system but also increase the unexpected read-write dependency.Next,we reallocate the reg-isters by weight order in turn to loosen the RAW dependencies.Furthermore,we use the NOP operation to pad the instructions with a minimal distance value of 2.Experiment results showed that the average distance of RAW dependencies was increased by over 20%.展开更多
基金This work was supported by the General Project of Humanities and Social Sciences Research of the Ministry of Education(16YJA740039,Sheng Xiao,2016)the Foundation Project of Philosophy and Social Science of Hunan(17YBA115,Sheng Xiao,2018).
文摘Timing speculative(TS)architecture is promising for improving the energy efficiency of microprocessors.Error recovery units,designed for tolerating occasional timing errors,have been used to support a wider range of voltage scaling,therefore to achieve a better energy efficiency.More specifically,the timing error rate,influenced mainly by data forwarding,is the bottleneck for voltage down-scaling in TS processors.In this paper,a new Timing Error Aware Register Allocation method is proposed.First,we designed the Dependency aware Interference Graph(DIG)construction to get the information of Read after Write(RAW)in programs.To build the construction,we get the disassemble code as input and suppose that there are unlimited registers,the same way as so-called virtual registers in many compilers.Then we change the disassemble codes to the SSA form for each basic block to make sure the registers are defined only once.Based on the DIG construction,registers were real-located to eliminate the timing error,by loosening the RAW dependencies.We con-struct the DIG for each function of the program and sort the edge of DIG by an increasing weight order.Since a smaller weighted-edge value means that its owner nodes have more frequent access in instruction flows,we expect it in different registers with no read-write dependency.At the same time,we make sure that there are no additional new spill codes emerging in our algorithm to minimize the rate of spill code.A high rate of spill code will not only decrease the performance of the system but also increase the unexpected read-write dependency.Next,we reallocate the reg-isters by weight order in turn to loosen the RAW dependencies.Furthermore,we use the NOP operation to pad the instructions with a minimal distance value of 2.Experiment results showed that the average distance of RAW dependencies was increased by over 20%.
