Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also propose...Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also proposed,which can adjust duty cycle of MOS switch in power clock generator depending on logic complexity and operating frequency to achieve optimum energy efficiency.Closed-form results are derived,which facilitate efficiency-optimized design of the power clock generator.An ERTL PLA and a conventional PLA are designed and simulated on 0.35μm process.The energy efficiency of the proposed power clock generator can reach 77%～85% operating between 20～100MHz.Simulation results indicate that ERTL is a low energy logic.Including power loss of power clock circuits,ERTL PLA still shows 65%～77% power savings compared to conventional PLA.展开更多
Purpose-The real-time generation of feature descriptors for object recognition is a challenging problem.In this research,the purpose of this paper is to provide a hardware friendly framework to generate sparse feature...Purpose-The real-time generation of feature descriptors for object recognition is a challenging problem.In this research,the purpose of this paper is to provide a hardware friendly framework to generate sparse features that can be useful for key feature point selection,feature extraction,and descriptor construction.The inspiration is drawn from feature formation processes of the human brain,taking into account the sparse,modular,and hierarchical processing of visual information.Design/methodology/approach-A sparse set of neurons referred as active neurons determines the feature points necessary for high-level vision applications such as object recognition.A psycho-physical mechanism of human low-level vision relates edge detection to noticeable local spatial stimuli,representing this set of active neurons.A cognitive memory cell array-based implementation of low-level vision is proposed.Applications of memory cell in edge detection are used for realizing human vision inspired feature selection and leading to feature vector construction for high-level vision applications.Findings-True parallel architecture and faster response of cognitive circuits avoid time costly and redundant feature extraction steps.Validation of proposed feature vector toward high-level computer vision applications is demonstrated using standard object recognition databases.The comparison against existing state-of-the-art object recognition features and methods shows an accuracy of 97,95,69 percent for Columbia Object Image Library-100,ALOI,and PASCAL VOC 2007 databases indicating an increase from benchmark methods by 5,3 and 10 percent,respectively.Originality/value-A hardware friendly low-level sparse edge feature processing system isproposed for recognizing objects.The edge features are developed based on threshold logic of neurons,and the sparse selection of the features applies a modular and hierarchical processing inspired from the human neural system.展开更多
A novel energy recovery logic style ERCCL （energy recovery capacitance coupling logic） , which has good energy performance compared to the conventional CMOS logic and other advanced energy recovery logic, is propose...A novel energy recovery logic style ERCCL （energy recovery capacitance coupling logic） , which has good energy performance compared to the conventional CMOS logic and other advanced energy recovery logic, is proposed. ERCCL uses capacitance coupling to perform a logic function, so it can energy-efficiently implement a high fan-in complex logic in a single gate. ERCCL is also a type of threshold logic. The gate count of a system based on ERCCL can be significantly reduced,which,in turn,will decrease the energy loss. A threshold logic synthesis methodology for ERCCL is also presented. MCNC benchmarks are run through the proposed synthesis methodology. The results indicate that about an 80% reduction in gate count can be obtained when compared with the synthesis results of SIS.展开更多
Autonomous lane keeping is an important technology in intelligent transportation,which is used to avoid unnecessary traffic accidents caused by lane departure.To adapt different lighting environment,and make up ordina...Autonomous lane keeping is an important technology in intelligent transportation,which is used to avoid unnecessary traffic accidents caused by lane departure.To adapt different lighting environment,and make up ordinary Hough transform’s shortcomings of tardiness and poor immunity,we propose an improved algorithm by using adaptive gray threshold and setting Region of interest(ROI),to do the quick Hough transform for tracking lane line,implementing autonomous lane keeping. The dynamic adaptive threshold method can be suitable with different lighting conditions and quickly,accurately remove most of the information not relative to lane line.Meanwhile setting ROI can let the program only care about the specific region which can provide useful information and further reduce the processing data.And then on the basic of identification,we put forward some efficient innovation strategy about the control logic of straight state,curve state and the transition state.The experiment proves that this solution greatly raises efficiency.展开更多
This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the perfo...This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.展开更多
文摘Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also proposed,which can adjust duty cycle of MOS switch in power clock generator depending on logic complexity and operating frequency to achieve optimum energy efficiency.Closed-form results are derived,which facilitate efficiency-optimized design of the power clock generator.An ERTL PLA and a conventional PLA are designed and simulated on 0.35μm process.The energy efficiency of the proposed power clock generator can reach 77%～85% operating between 20～100MHz.Simulation results indicate that ERTL is a low energy logic.Including power loss of power clock circuits,ERTL PLA still shows 65%～77% power savings compared to conventional PLA.
文摘Purpose-The real-time generation of feature descriptors for object recognition is a challenging problem.In this research,the purpose of this paper is to provide a hardware friendly framework to generate sparse features that can be useful for key feature point selection,feature extraction,and descriptor construction.The inspiration is drawn from feature formation processes of the human brain,taking into account the sparse,modular,and hierarchical processing of visual information.Design/methodology/approach-A sparse set of neurons referred as active neurons determines the feature points necessary for high-level vision applications such as object recognition.A psycho-physical mechanism of human low-level vision relates edge detection to noticeable local spatial stimuli,representing this set of active neurons.A cognitive memory cell array-based implementation of low-level vision is proposed.Applications of memory cell in edge detection are used for realizing human vision inspired feature selection and leading to feature vector construction for high-level vision applications.Findings-True parallel architecture and faster response of cognitive circuits avoid time costly and redundant feature extraction steps.Validation of proposed feature vector toward high-level computer vision applications is demonstrated using standard object recognition databases.The comparison against existing state-of-the-art object recognition features and methods shows an accuracy of 97,95,69 percent for Columbia Object Image Library-100,ALOI,and PASCAL VOC 2007 databases indicating an increase from benchmark methods by 5,3 and 10 percent,respectively.Originality/value-A hardware friendly low-level sparse edge feature processing system isproposed for recognizing objects.The edge features are developed based on threshold logic of neurons,and the sparse selection of the features applies a modular and hierarchical processing inspired from the human neural system.
文摘A novel energy recovery logic style ERCCL （energy recovery capacitance coupling logic） , which has good energy performance compared to the conventional CMOS logic and other advanced energy recovery logic, is proposed. ERCCL uses capacitance coupling to perform a logic function, so it can energy-efficiently implement a high fan-in complex logic in a single gate. ERCCL is also a type of threshold logic. The gate count of a system based on ERCCL can be significantly reduced,which,in turn,will decrease the energy loss. A threshold logic synthesis methodology for ERCCL is also presented. MCNC benchmarks are run through the proposed synthesis methodology. The results indicate that about an 80% reduction in gate count can be obtained when compared with the synthesis results of SIS.
文摘Autonomous lane keeping is an important technology in intelligent transportation,which is used to avoid unnecessary traffic accidents caused by lane departure.To adapt different lighting environment,and make up ordinary Hough transform’s shortcomings of tardiness and poor immunity,we propose an improved algorithm by using adaptive gray threshold and setting Region of interest(ROI),to do the quick Hough transform for tracking lane line,implementing autonomous lane keeping. The dynamic adaptive threshold method can be suitable with different lighting conditions and quickly,accurately remove most of the information not relative to lane line.Meanwhile setting ROI can let the program only care about the specific region which can provide useful information and further reduce the processing data.And then on the basic of identification,we put forward some efficient innovation strategy about the control logic of straight state,curve state and the transition state.The experiment proves that this solution greatly raises efficiency.
文摘This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.
