为实现XML数据库的性能评测,提出基于TPC-C的XML数据库测试方案。针对XML数据库特性,对其数据结构、查询事务语句进行定制,将原有9张表映射成5个XML Schema文件,按照SQL/XML标准重写负载事务。应用该方案对SQL Server 2005数据库进行测...为实现XML数据库的性能评测,提出基于TPC-C的XML数据库测试方案。针对XML数据库特性,对其数据结构、查询事务语句进行定制,将原有9张表映射成5个XML Schema文件,按照SQL/XML标准重写负载事务。应用该方案对SQL Server 2005数据库进行测试,结果表明显示的各项事务特征均与TPC-C基准相同。展开更多
Itanium is the first generation product processor based on IA-64 architecture. ORC(Open Research Compil-er )provides an open source IPF(Itanium Processor Family)research compiler infrastructure. We have compiled andru...Itanium is the first generation product processor based on IA-64 architecture. ORC(Open Research Compil-er )provides an open source IPF(Itanium Processor Family)research compiler infrastructure. We have compiled andrun NAS Benchmarks on the Itanium machine. This paper briefly describes the performance of orcc, sgicc and gcc inthe following 3 ways: execution time, compilation time, and executable file size. The results show that orcc has near-ly the same performance as sgicc, which is 2 fold faster over gcc in the aspect of execution time. We also find that evenwith the best-optimized program, the utilization ratio of process resources is no more that 70%.展开更多
System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to opti...System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to optimize the test data volume, decrease the testing time, and conquer the ATE memory limitation for SOC designs. This paper presents a new compression method of testing for intellectual property core-based system-on-chip. The proposed method is based on new split- data variable length (SDV) codes that are designed using the split-options along with identification bits in a string of test data. This paper analyses the reduction of test data volume, testing time, run time, size of memory required in ATE and improvement of compression ratio. Experimental results for ISCAS 85 and ISCAS 89 Benchmark circuits show that SDV codes outperform other compression methods with the best compression ratio for test data compression. The decompression architecture for SDV codes is also presented for decoding the implementations of compressed bits. The proposed scheme shows that SDV codes are accessible to any of the variations in the input test data stream.展开更多
文摘为实现XML数据库的性能评测,提出基于TPC-C的XML数据库测试方案。针对XML数据库特性,对其数据结构、查询事务语句进行定制,将原有9张表映射成5个XML Schema文件,按照SQL/XML标准重写负载事务。应用该方案对SQL Server 2005数据库进行测试,结果表明显示的各项事务特征均与TPC-C基准相同。
文摘Itanium is the first generation product processor based on IA-64 architecture. ORC(Open Research Compil-er )provides an open source IPF(Itanium Processor Family)research compiler infrastructure. We have compiled andrun NAS Benchmarks on the Itanium machine. This paper briefly describes the performance of orcc, sgicc and gcc inthe following 3 ways: execution time, compilation time, and executable file size. The results show that orcc has near-ly the same performance as sgicc, which is 2 fold faster over gcc in the aspect of execution time. We also find that evenwith the best-optimized program, the utilization ratio of process resources is no more that 70%.
文摘System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to optimize the test data volume, decrease the testing time, and conquer the ATE memory limitation for SOC designs. This paper presents a new compression method of testing for intellectual property core-based system-on-chip. The proposed method is based on new split- data variable length (SDV) codes that are designed using the split-options along with identification bits in a string of test data. This paper analyses the reduction of test data volume, testing time, run time, size of memory required in ATE and improvement of compression ratio. Experimental results for ISCAS 85 and ISCAS 89 Benchmark circuits show that SDV codes outperform other compression methods with the best compression ratio for test data compression. The decompression architecture for SDV codes is also presented for decoding the implementations of compressed bits. The proposed scheme shows that SDV codes are accessible to any of the variations in the input test data stream.
