在超宽带(UWB)通信中,跳时冲激无线电(TH-IR)技术具有系统结构简单、成本低、功率小等优点,得到广泛的研究及应用探索。基于TH-IR UWB技术,提出了一种能够保证链路误码率及传输速率的自适应速率跳时(Rate-Adaptive Time Hopping,RATH)...在超宽带(UWB)通信中,跳时冲激无线电(TH-IR)技术具有系统结构简单、成本低、功率小等优点,得到广泛的研究及应用探索。基于TH-IR UWB技术,提出了一种能够保证链路误码率及传输速率的自适应速率跳时(Rate-Adaptive Time Hopping,RATH)介质访问控制(MAC)协议,该协议利用跳时码管理多用户的信道访问,依据接收节点的信干比控制链路的建立,并采用自适应速率算法调节链路的传输速率。NS2平台下的仿真实验表明,与U-MAC等已有的固定速率协议相比较,RATH MAC协议能够使网络有效吞吐量和传输时延得到明显改善。展开更多
A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off-...A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off- set cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm^2.展开更多
文摘在超宽带(UWB)通信中,跳时冲激无线电(TH-IR)技术具有系统结构简单、成本低、功率小等优点,得到广泛的研究及应用探索。基于TH-IR UWB技术,提出了一种能够保证链路误码率及传输速率的自适应速率跳时(Rate-Adaptive Time Hopping,RATH)介质访问控制(MAC)协议,该协议利用跳时码管理多用户的信道访问,依据接收节点的信干比控制链路的建立,并采用自适应速率算法调节链路的传输速率。NS2平台下的仿真实验表明,与U-MAC等已有的固定速率协议相比较,RATH MAC协议能够使网络有效吞吐量和传输时延得到明显改善。
基金supported by the National High Technology Research and Development Program of China(No.2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University.
文摘A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off- set cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm^2.
