Capacitor-less 2T0C dynamic random-access memory(DRAM)employing oxide semiconductors(OSs)as a channel has great potential in the development of highly scaled three dimensional(3D)-structured devices.However,the use of...Capacitor-less 2T0C dynamic random-access memory(DRAM)employing oxide semiconductors(OSs)as a channel has great potential in the development of highly scaled three dimensional(3D)-structured devices.However,the use of OS and such device structures presents certain challenges,including the trade-off relationship between the field-effect mobility and stability of OSs.Conventional 4-line-based operation of the 2T0C enlarges the entire cell volume and complicates the peripheral circuit.Herein,we proposed an IGO(In-Ga-O)channel 2-line-based 2T0C cell design and operating sequences comparable to those of the conventional Si-channel 1 T1C DRAM.IGO was adopted to achieve high thermal stability above 800℃,and the process conditions were optimized to simultaneously obtain a high μFE of 90.7 cm^(2)·V^(-)1·s^(-1),positive Vth of 0.34 V,superior reliability,and uniformity.The proposed 2-line-based 2T0C DRAM cell successfully exhibited multi-bit operation,with the stored voltage varying from 0 V to 1 V at 0.1 V intervals.Furthermore,for stored voltage intervals of 0.1 V and 0.5 V,the refresh time was 10 s and 1000 s in multi-bit operation;these values were more than 150 and 15000 times longer than those of the conventional Si channel 1T1C DRAM,respectively.A monolithic stacked 2-line-based 2T0C DRAM was fabricated,and a multi-bit operation was confirmed.展开更多
DRAM作为计算机存储系统的核心组件,在HPC、云计算、AI等领域至关重要。然而,传统1T1C DRAM受电容缩放瓶颈、刷新功耗及制造复杂度等问题限制,难以满足先进制程需求。2T0C DRAM采用双晶体管架构,利用浮体效应、栅极耦合等机制存储电荷,...DRAM作为计算机存储系统的核心组件,在HPC、云计算、AI等领域至关重要。然而,传统1T1C DRAM受电容缩放瓶颈、刷新功耗及制造复杂度等问题限制,难以满足先进制程需求。2T0C DRAM采用双晶体管架构,利用浮体效应、栅极耦合等机制存储电荷,实现高密度、低功耗及工艺兼容性提升。本研究分析2T0C DRAM的技术原理、结构设计及其相较于1T1C DRAM的优势,探讨数据保持、读写干扰、工艺变异等挑战,并综述器件优化、电路创新及先进制造工艺的应对策略。此外,结合CIM、3D集成等趋势,探讨其在HPC、嵌入式及新型存储中的应用价值。当前,三星、美光等厂商已展开2T0C DRAM研发,预计未来逐步进入量产。随着半导体工艺演进,2T0C DRAM有望成为下一代高密度、低功耗存储技术。然而,量子效应、工艺适配及产业链完善仍是关键挑战。未来研究将聚焦器件微缩、存算一体及异质集成,推动2T0C DRAM发展与产业化进程。As a core component of computer memory systems, DRAM plays a critical role in HPC, cloud computing, and AI. However, traditional 1T1C DRAM faces challenges such as capacitor scaling limitations, high refresh power consumption, and increasing fabrication complexity, restricting its scalability in advanced process nodes. To address these issues, 2T0C DRAM adopts a two-transistor architecture, utilizing floating-body effects and gate coupling mechanisms to store charge, thereby enhancing storage density, reducing power consumption, and improving process compatibility. This study analyzes the technical principles and structural design of 2T0C DRAM, highlighting its advantages over 1T1C DRAM while addressing challenges such as data retention, read/write disturbances, and process variations. Various optimization strategies, including device engineering, circuit design innovations, and advanced fabrication techniques, are also reviewed. Furthermore, considering emerging trends like CIM and 3D integration, we explore the potential applications of 2T0C DRAM in HPC, embedded systems, and next-generation memory technologies. Currently, leading memory manufacturers such as Samsung and Micron have initiated research on 2T0C DRAM, with commercialization expected in the near future. With the continuous advancement of semiconductor technology, 2T0C DRAM is poised to become a key candidate for next-generation high-density, low-power memory solutions. However, challenges such as quantum effects, process adaptation, and supply chain maturity remain critical. Future research will focus on device scaling, in-memory computing, and heterogeneous integration to accelerate the development and industrialization of 2T0C DRAM.展开更多
质子打靶时刻T0作为中国散裂中子源(Chinese Spallation Neutron Source,CSNS)多物理谱仪的初始触发信号,其高准确性和高稳定性是谱仪高效运行的前提和基础。在实验物理和工业控制系统(Experimental Physics and Industrial Control Sys...质子打靶时刻T0作为中国散裂中子源(Chinese Spallation Neutron Source,CSNS)多物理谱仪的初始触发信号,其高准确性和高稳定性是谱仪高效运行的前提和基础。在实验物理和工业控制系统(Experimental Physics and Industrial Control System,EPICS)平台上开发了一套CSNS多物理谱仪T0信号触发监测系统。T0信号接入T0扇出器标记高精度时间戳,采用高吞吐量的分布式发布订阅消息系统Kafka来实现大数据流量的削峰和异步通信。监测数据作为过程变量(Process Variable,PV)上传EPICS,利用Open-Falcon监控系统和可视化工具Grafana实现对数据的监测与可视化。该系统可以对T0信号的频率和T0在扇出与传输过程中的时间延迟进行实时监测,从而保证CSNS多物理谱仪的正常运行。展开更多
介绍了兰州重离子加速器冷却储存环(HIRFL-CSR)外靶实验中时间起点探测器(T0)的前端电子学原型模块的设计与测试。探索了基于过阈时间法和专用集成电路NINO芯片进行多气隙电阻板室探测器信号读出的模拟前端电路的设计技术,并实际完成了...介绍了兰州重离子加速器冷却储存环(HIRFL-CSR)外靶实验中时间起点探测器(T0)的前端电子学原型模块的设计与测试。探索了基于过阈时间法和专用集成电路NINO芯片进行多气隙电阻板室探测器信号读出的模拟前端电路的设计技术,并实际完成了原型电子学模块的设计。此模块共集成6个测量通道,可以进行前沿甄别及电荷时间变换。目前已经在实验室条件下完成了各项电子学性能测试,包括不同甄别阈值下的时间精度测试以及不同输入信号幅度下的输出脉宽测试。测试结果表明,在100 f C至2 p C的动态范围内,此模块时间精度好于20 ps,满足应用需求,这也为进一步的电子学系统设计做好了准备。展开更多
CCl_3SO_2Br used as a 'telogen' reacts with CH_2=CF_2 to give mainly the 'mono- adduct' CCl_3CH_2CF_2Br, together with very small amouats of CCl_3CF_2CH_2Br, CCl_2BrCH_2CF_2Br and the 'di-adduct...CCl_3SO_2Br used as a 'telogen' reacts with CH_2=CF_2 to give mainly the 'mono- adduct' CCl_3CH_2CF_2Br, together with very small amouats of CCl_3CF_2CH_2Br, CCl_2BrCH_2CF_2Br and the 'di-adduct' CCl_3(CH_2CF_2)_2Br. The result indicates that CCl_3SO_2Br can be used as an addendum in trichloromethyl-bromo-addition reactions to olefins.展开更多
基金supported by the Technology Innovation Program(Grant Nos.20017382 and 20023023)funded by the Ministry of Trade,Industry&Energy(MOTIE,Republic of Korea)supported by a National Research Foundation of Korea(NRF)grant funded by the Korean Government(MSIT)(Grant No.RS-2023-00260527).
文摘Capacitor-less 2T0C dynamic random-access memory(DRAM)employing oxide semiconductors(OSs)as a channel has great potential in the development of highly scaled three dimensional(3D)-structured devices.However,the use of OS and such device structures presents certain challenges,including the trade-off relationship between the field-effect mobility and stability of OSs.Conventional 4-line-based operation of the 2T0C enlarges the entire cell volume and complicates the peripheral circuit.Herein,we proposed an IGO(In-Ga-O)channel 2-line-based 2T0C cell design and operating sequences comparable to those of the conventional Si-channel 1 T1C DRAM.IGO was adopted to achieve high thermal stability above 800℃,and the process conditions were optimized to simultaneously obtain a high μFE of 90.7 cm^(2)·V^(-)1·s^(-1),positive Vth of 0.34 V,superior reliability,and uniformity.The proposed 2-line-based 2T0C DRAM cell successfully exhibited multi-bit operation,with the stored voltage varying from 0 V to 1 V at 0.1 V intervals.Furthermore,for stored voltage intervals of 0.1 V and 0.5 V,the refresh time was 10 s and 1000 s in multi-bit operation;these values were more than 150 and 15000 times longer than those of the conventional Si channel 1T1C DRAM,respectively.A monolithic stacked 2-line-based 2T0C DRAM was fabricated,and a multi-bit operation was confirmed.
文摘DRAM作为计算机存储系统的核心组件,在HPC、云计算、AI等领域至关重要。然而,传统1T1C DRAM受电容缩放瓶颈、刷新功耗及制造复杂度等问题限制,难以满足先进制程需求。2T0C DRAM采用双晶体管架构,利用浮体效应、栅极耦合等机制存储电荷,实现高密度、低功耗及工艺兼容性提升。本研究分析2T0C DRAM的技术原理、结构设计及其相较于1T1C DRAM的优势,探讨数据保持、读写干扰、工艺变异等挑战,并综述器件优化、电路创新及先进制造工艺的应对策略。此外,结合CIM、3D集成等趋势,探讨其在HPC、嵌入式及新型存储中的应用价值。当前,三星、美光等厂商已展开2T0C DRAM研发,预计未来逐步进入量产。随着半导体工艺演进,2T0C DRAM有望成为下一代高密度、低功耗存储技术。然而,量子效应、工艺适配及产业链完善仍是关键挑战。未来研究将聚焦器件微缩、存算一体及异质集成,推动2T0C DRAM发展与产业化进程。As a core component of computer memory systems, DRAM plays a critical role in HPC, cloud computing, and AI. However, traditional 1T1C DRAM faces challenges such as capacitor scaling limitations, high refresh power consumption, and increasing fabrication complexity, restricting its scalability in advanced process nodes. To address these issues, 2T0C DRAM adopts a two-transistor architecture, utilizing floating-body effects and gate coupling mechanisms to store charge, thereby enhancing storage density, reducing power consumption, and improving process compatibility. This study analyzes the technical principles and structural design of 2T0C DRAM, highlighting its advantages over 1T1C DRAM while addressing challenges such as data retention, read/write disturbances, and process variations. Various optimization strategies, including device engineering, circuit design innovations, and advanced fabrication techniques, are also reviewed. Furthermore, considering emerging trends like CIM and 3D integration, we explore the potential applications of 2T0C DRAM in HPC, embedded systems, and next-generation memory technologies. Currently, leading memory manufacturers such as Samsung and Micron have initiated research on 2T0C DRAM, with commercialization expected in the near future. With the continuous advancement of semiconductor technology, 2T0C DRAM is poised to become a key candidate for next-generation high-density, low-power memory solutions. However, challenges such as quantum effects, process adaptation, and supply chain maturity remain critical. Future research will focus on device scaling, in-memory computing, and heterogeneous integration to accelerate the development and industrialization of 2T0C DRAM.
文摘质子打靶时刻T0作为中国散裂中子源(Chinese Spallation Neutron Source,CSNS)多物理谱仪的初始触发信号,其高准确性和高稳定性是谱仪高效运行的前提和基础。在实验物理和工业控制系统(Experimental Physics and Industrial Control System,EPICS)平台上开发了一套CSNS多物理谱仪T0信号触发监测系统。T0信号接入T0扇出器标记高精度时间戳,采用高吞吐量的分布式发布订阅消息系统Kafka来实现大数据流量的削峰和异步通信。监测数据作为过程变量(Process Variable,PV)上传EPICS,利用Open-Falcon监控系统和可视化工具Grafana实现对数据的监测与可视化。该系统可以对T0信号的频率和T0在扇出与传输过程中的时间延迟进行实时监测,从而保证CSNS多物理谱仪的正常运行。
文摘介绍了兰州重离子加速器冷却储存环(HIRFL-CSR)外靶实验中时间起点探测器(T0)的前端电子学原型模块的设计与测试。探索了基于过阈时间法和专用集成电路NINO芯片进行多气隙电阻板室探测器信号读出的模拟前端电路的设计技术,并实际完成了原型电子学模块的设计。此模块共集成6个测量通道,可以进行前沿甄别及电荷时间变换。目前已经在实验室条件下完成了各项电子学性能测试,包括不同甄别阈值下的时间精度测试以及不同输入信号幅度下的输出脉宽测试。测试结果表明,在100 f C至2 p C的动态范围内,此模块时间精度好于20 ps,满足应用需求,这也为进一步的电子学系统设计做好了准备。
文摘CCl_3SO_2Br used as a 'telogen' reacts with CH_2=CF_2 to give mainly the 'mono- adduct' CCl_3CH_2CF_2Br, together with very small amouats of CCl_3CF_2CH_2Br, CCl_2BrCH_2CF_2Br and the 'di-adduct' CCl_3(CH_2CF_2)_2Br. The result indicates that CCl_3SO_2Br can be used as an addendum in trichloromethyl-bromo-addition reactions to olefins.
