Sensor noise is a critical factor that degrades the performance of image processing systems.In traditional computing systems,noise correction is implemented in the digital domain,resulting in redundant latency and pow...Sensor noise is a critical factor that degrades the performance of image processing systems.In traditional computing systems,noise correction is implemented in the digital domain,resulting in redundant latency and power consumption overhead in the analog-to-digital conversion.In this work,we propose an analog-domain image correction architecture based on a proposed small-scale UNet,which implements a compact noise correction network within a one-transistor-one-memristor(1T1R)array.The statistical non-idealities of the fabricated 1T1R array(e.g.,device variability)are rigorously incorporated into the network's training and inference simulations.This correction network architecture leverages memristors for conducting multiply-accumulate operations aimed at rectifying non-uniform noise,defective pixels(stuck-at-bright/dark),and exposure mismatch.Compared to systems without correction,the proposed architecture achieves up to 50.13%improvement in recognition accuracy while demonstrating robust tolerance to memristor device-level errors.The proposed system achieves a 2.13-fold latency reduction and three orders of magnitude higher energy efficiency compared to conventional architecture.This work establishes a new paradigm for advancing the development of low-power,low-latency,and high-precision image processing systems.展开更多
基于忆阻器阵列的类脑电路为实现高能效神经网络计算提供了极具潜力的技术路线.然而,现有方案通常需要使用大量的模数转换过程,成为计算电路能效进一步提升的瓶颈.因此,提出了一种基于1T1R(1 Transistor 1 Resistor)忆阻器交叉阵列与CMO...基于忆阻器阵列的类脑电路为实现高能效神经网络计算提供了极具潜力的技术路线.然而,现有方案通常需要使用大量的模数转换过程,成为计算电路能效进一步提升的瓶颈.因此,提出了一种基于1T1R(1 Transistor 1 Resistor)忆阻器交叉阵列与CMOS(Complementary Metal-Oxide-Semiconductor)激活函数的全模拟神经网络架构,以及与其相关的训练优化方法 .该架构采用1T1R忆阻器交叉阵列来实现神经网络线性层中的模拟计算,同时利用CMOS非线性电路来实现神经网络激活层的模拟计算,在全模拟域实现神经网络大幅减少了模数转换器的使用,优化了能效和面积成本.实验结果验证了忆阻器作为神经网络权重层的可行性,同时设计多种CMOS模拟电路,在模拟域实现了多种非线性激活函数,如伪ReLU(Rectified Linear Unit)、伪Sigmoid、伪Tanh、伪Softmax等电路.通过定制化训练方法来优化模拟电路神经网络的训练过程,解决了实际非线性电路的输出饱和条件下的训练问题.仿真结果表明,即使在模拟电路的激活函数与理想激活函数不一致的情况下,全模拟神经网络电路在MNIST(Modified National Institute of Standards and Technology)手写数字识别任务中的识别率仍然可以达到98%,可与基于软件的标准网络模型的结果相比.展开更多
基金Project supported by the National Key Research and Development Program of China(Grant No.2024YFA1208800)the National Natural Science Foundation of China(Grant Nos.62404253,62304254,U23A20322)。
文摘Sensor noise is a critical factor that degrades the performance of image processing systems.In traditional computing systems,noise correction is implemented in the digital domain,resulting in redundant latency and power consumption overhead in the analog-to-digital conversion.In this work,we propose an analog-domain image correction architecture based on a proposed small-scale UNet,which implements a compact noise correction network within a one-transistor-one-memristor(1T1R)array.The statistical non-idealities of the fabricated 1T1R array(e.g.,device variability)are rigorously incorporated into the network's training and inference simulations.This correction network architecture leverages memristors for conducting multiply-accumulate operations aimed at rectifying non-uniform noise,defective pixels(stuck-at-bright/dark),and exposure mismatch.Compared to systems without correction,the proposed architecture achieves up to 50.13%improvement in recognition accuracy while demonstrating robust tolerance to memristor device-level errors.The proposed system achieves a 2.13-fold latency reduction and three orders of magnitude higher energy efficiency compared to conventional architecture.This work establishes a new paradigm for advancing the development of low-power,low-latency,and high-precision image processing systems.
文摘基于广义约化R矩阵理论,使用RAC程序(R-matrix analysis code)综合分析了^(6)He系统中所有可以利用的实验数据,给出了氚核入射10-2—20 MeV能量范围内主要反应道的评价核数据.其中积分截面包括T(t,2n)^(4)He,T(t,n)^(5)He,T(t,d)^(4)H;微分截面包括T(t,2n)^(4)He,T(t,n)^(5)He,T(t,d)^(4)H,T(t,t)T.结果表明,RAC的评价结果与实验数据和ENDF/B-Ⅷ.1的评价数据整体符合良好.重点关注T(t,2n)^(4)He反应,评价值在10^(-2)—20 MeV范围内与已有实验数据一致,在2.9 Me V附近出现由2+能级主导的共振,在1.9 Me V处,已有实验同时测量了积分截面和角分布,本工作的评价结果在两类数据上均表现出良好的一致性,积分截面与微分截面的联合约束有效提升了R矩阵参数的稳定性和评价结果的可靠性.基于6He系统的整体评价,进一步补充了T(t,n)^(5)He和T(t,d)^(4)H反应的截面数据.本工作完善了聚变反应相关的数据基础,并为后续与镜像系统6Be系统的联合分析奠定了基础.
文摘基于忆阻器阵列的类脑电路为实现高能效神经网络计算提供了极具潜力的技术路线.然而,现有方案通常需要使用大量的模数转换过程,成为计算电路能效进一步提升的瓶颈.因此,提出了一种基于1T1R(1 Transistor 1 Resistor)忆阻器交叉阵列与CMOS(Complementary Metal-Oxide-Semiconductor)激活函数的全模拟神经网络架构,以及与其相关的训练优化方法 .该架构采用1T1R忆阻器交叉阵列来实现神经网络线性层中的模拟计算,同时利用CMOS非线性电路来实现神经网络激活层的模拟计算,在全模拟域实现神经网络大幅减少了模数转换器的使用,优化了能效和面积成本.实验结果验证了忆阻器作为神经网络权重层的可行性,同时设计多种CMOS模拟电路,在模拟域实现了多种非线性激活函数,如伪ReLU(Rectified Linear Unit)、伪Sigmoid、伪Tanh、伪Softmax等电路.通过定制化训练方法来优化模拟电路神经网络的训练过程,解决了实际非线性电路的输出饱和条件下的训练问题.仿真结果表明,即使在模拟电路的激活函数与理想激活函数不一致的情况下,全模拟神经网络电路在MNIST(Modified National Institute of Standards and Technology)手写数字识别任务中的识别率仍然可以达到98%,可与基于软件的标准网络模型的结果相比.
