Because the small CACHE size of computers, the scanning speed of DFA based multi-pattern string-matching algorithms slows down rapidly especially when the number of patterns is very large. For solving such problems, w...Because the small CACHE size of computers, the scanning speed of DFA based multi-pattern string-matching algorithms slows down rapidly especially when the number of patterns is very large. For solving such problems, we cut down the scanning time of those algorithms (i.e. DFA based) by rearranging the states table and shrinking the DFA alphabet size. Both the methods can decrease the probability of large-scale random memory accessing and increase the probability of continuously memory accessing. Then the hitting rate of the CACHE is increased and the searching time of on the DFA is reduced. Shrinking the alphabet size of the DFA also reduces the storage complication. The AC++algorithm, by optimizing the Aho-Corasick (i.e. AC) algorithm using such methods, proves the theoretical analysis. And the experimentation results show that the scanning time of AC++and the storage occupied is better than that of AC in most cases and the result is much attractive when the number of patterns is very large. Because DFA is a widely used base algorithm in may string matching algorithms, such as DAWG, SBOM etc., the optimizing method discussed is significant in practice.展开更多
As the demand for energy efficiency rises,researchers are increasingly prioritizing the quest for energy-efficient chip design.Superconducting SFQ circuit technology has garnered attention due to its ultra-high speed ...As the demand for energy efficiency rises,researchers are increasingly prioritizing the quest for energy-efficient chip design.Superconducting SFQ circuit technology has garnered attention due to its ultra-high speed and low power consumption characteristics.In this paper,we propose a layout method called Maximum Operating Frequency Constraint(MOFC)for SFQ circuit design.Using this method,we demonstrated a 32-bit bit-parallel string-matching processor fabricated based on SIMIT-Nb03P technology,which holds practical value.The MOFC method focuses on achieving high bit-width processor design within constrained area cost in SFQ circuits,contributing to less energy consumption.To the best of our knowledge,this represents the first demonstrated instance of a superconducting SFQ chip achieving successful internal 32-bit data parallel processing.Our chip has been fabricated and tested,revealing not only its capability for 32-bit bit-parallel processing at a high speed of 12 GHz but also its achievement of an energy efficiency ratio of up to 251 GOPS/W.展开更多
文摘Because the small CACHE size of computers, the scanning speed of DFA based multi-pattern string-matching algorithms slows down rapidly especially when the number of patterns is very large. For solving such problems, we cut down the scanning time of those algorithms (i.e. DFA based) by rearranging the states table and shrinking the DFA alphabet size. Both the methods can decrease the probability of large-scale random memory accessing and increase the probability of continuously memory accessing. Then the hitting rate of the CACHE is increased and the searching time of on the DFA is reduced. Shrinking the alphabet size of the DFA also reduces the storage complication. The AC++algorithm, by optimizing the Aho-Corasick (i.e. AC) algorithm using such methods, proves the theoretical analysis. And the experimentation results show that the scanning time of AC++and the storage occupied is better than that of AC in most cases and the result is much attractive when the number of patterns is very large. Because DFA is a widely used base algorithm in may string matching algorithms, such as DAWG, SBOM etc., the optimizing method discussed is significant in practice.
文摘As the demand for energy efficiency rises,researchers are increasingly prioritizing the quest for energy-efficient chip design.Superconducting SFQ circuit technology has garnered attention due to its ultra-high speed and low power consumption characteristics.In this paper,we propose a layout method called Maximum Operating Frequency Constraint(MOFC)for SFQ circuit design.Using this method,we demonstrated a 32-bit bit-parallel string-matching processor fabricated based on SIMIT-Nb03P technology,which holds practical value.The MOFC method focuses on achieving high bit-width processor design within constrained area cost in SFQ circuits,contributing to less energy consumption.To the best of our knowledge,this represents the first demonstrated instance of a superconducting SFQ chip achieving successful internal 32-bit data parallel processing.Our chip has been fabricated and tested,revealing not only its capability for 32-bit bit-parallel processing at a high speed of 12 GHz but also its achievement of an energy efficiency ratio of up to 251 GOPS/W.
