Complementary metal oxide semiconductor(CMOS)aging mechanisms including bias temperature instability(BTI)pose growing concerns about circuit reliability.BTI results in threshold voltage increases on CMOS transistors,c...Complementary metal oxide semiconductor(CMOS)aging mechanisms including bias temperature instability(BTI)pose growing concerns about circuit reliability.BTI results in threshold voltage increases on CMOS transistors,causing delay shifts and timing violations on logic circuits.The amount of degradation is dependent on the circuit workload,which increases the challenge for accurate BTI aging prediction at the design time.In this paper,a BTI prediction method for logic circuits based on statistical static timing analysis(SSTA)is proposed,especially considering the correlation between circuit workload and BTI degradation.It consists of a training phase,to discover the relationship between circuit scale and the required workload samples,and a prediction phase,to present the degradations under different workloads in Gaussian probability distributions.This method can predict the distribution of degradations with negligible errors,and identify 50%more BTI-critical paths in an affordable time,compared with conventional methods.展开更多
As semiconductor technology continues to develop,fragment integration levels are constantly increasing,principal to smaller and more complex electronic devices.However,concurrently,factors such as process variations a...As semiconductor technology continues to develop,fragment integration levels are constantly increasing,principal to smaller and more complex electronic devices.However,concurrently,factors such as process variations and device aging are gradually revealing their significant impact on circuit reliability.These factors not only pose challenges in circuit design and production but also represent potential threats to the performance and lifespan of electronic devices.Traditional analysismethods are no longer practical in scenarios of increasing integration levels,leading to unacceptable performance losses.In contrast,processvariation and aging-aware Static Timing Analysis(STA)offer design engineers a way to accurately estimate statistical delay distributions and assess the impact of these factors.However,STA is both expensive and complex,relying on intensive Monte Carlo simulations and requiring access to confidential,physics-based circuit aging models to generate the necessary standard cell libraries.This paper introduces a novel application of Graph Neural Networks(GNN)for the precise estimation of process variations and device aging effects on circuit delay along any path.The proposed Re-GNN framework enables design engineers to perform reliability estimation more efficiently,eliminating the need for transistor models,standard cell libraries,or even STA.Extensive experiments demonstrate successful estimation of delay degradation for all paths in EPFL and ITC-99 benchmark tests.These findings present a fresh approach to address circuit reliability concerns,providing potential solutions to ensure the performance and reliability of electronic devices amid ongoing advancements in semiconductor technology.展开更多
To achieve a characterization method for the gate delay library used in block based statistical static timing analysis with neither unacceptably poor accuracy nor forbiddingly high cost,we found that general-purpose g...To achieve a characterization method for the gate delay library used in block based statistical static timing analysis with neither unacceptably poor accuracy nor forbiddingly high cost,we found that general-purpose gate delay models are useful as intermediaries between the circuit simulation data and the gate delay models in required forms.In this work,two gate delay models for process variation considering different driving and loading conditions are proposed.From the testing results,these two models,especially the one that combines effective dimension reduction（EDR） from statistics society with comprehensive gate delay models,offer good accuracy with low characterization cost,and they are thus competent for use in statistical timing analysis（SSTA）.In addition, these two models have their own value in other SSTA techniques.展开更多
基金3the High Performance Computing Center of Shanghai University,Shanghai Engineering Research Center of Intelligent Computing System(19DZ2252600)supported by State Key Laboratory of Computer Architecture(Institute of Computing Technology,Chinese Academy of Sciences)(CARCH201909)。
文摘Complementary metal oxide semiconductor(CMOS)aging mechanisms including bias temperature instability(BTI)pose growing concerns about circuit reliability.BTI results in threshold voltage increases on CMOS transistors,causing delay shifts and timing violations on logic circuits.The amount of degradation is dependent on the circuit workload,which increases the challenge for accurate BTI aging prediction at the design time.In this paper,a BTI prediction method for logic circuits based on statistical static timing analysis(SSTA)is proposed,especially considering the correlation between circuit workload and BTI degradation.It consists of a training phase,to discover the relationship between circuit scale and the required workload samples,and a prediction phase,to present the degradations under different workloads in Gaussian probability distributions.This method can predict the distribution of degradations with negligible errors,and identify 50%more BTI-critical paths in an affordable time,compared with conventional methods.
文摘As semiconductor technology continues to develop,fragment integration levels are constantly increasing,principal to smaller and more complex electronic devices.However,concurrently,factors such as process variations and device aging are gradually revealing their significant impact on circuit reliability.These factors not only pose challenges in circuit design and production but also represent potential threats to the performance and lifespan of electronic devices.Traditional analysismethods are no longer practical in scenarios of increasing integration levels,leading to unacceptable performance losses.In contrast,processvariation and aging-aware Static Timing Analysis(STA)offer design engineers a way to accurately estimate statistical delay distributions and assess the impact of these factors.However,STA is both expensive and complex,relying on intensive Monte Carlo simulations and requiring access to confidential,physics-based circuit aging models to generate the necessary standard cell libraries.This paper introduces a novel application of Graph Neural Networks(GNN)for the precise estimation of process variations and device aging effects on circuit delay along any path.The proposed Re-GNN framework enables design engineers to perform reliability estimation more efficiently,eliminating the need for transistor models,standard cell libraries,or even STA.Extensive experiments demonstrate successful estimation of delay degradation for all paths in EPFL and ITC-99 benchmark tests.These findings present a fresh approach to address circuit reliability concerns,providing potential solutions to ensure the performance and reliability of electronic devices amid ongoing advancements in semiconductor technology.
文摘To achieve a characterization method for the gate delay library used in block based statistical static timing analysis with neither unacceptably poor accuracy nor forbiddingly high cost,we found that general-purpose gate delay models are useful as intermediaries between the circuit simulation data and the gate delay models in required forms.In this work,two gate delay models for process variation considering different driving and loading conditions are proposed.From the testing results,these two models,especially the one that combines effective dimension reduction（EDR） from statistics society with comprehensive gate delay models,offer good accuracy with low characterization cost,and they are thus competent for use in statistical timing analysis（SSTA）.In addition, these two models have their own value in other SSTA techniques.
