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3-D SPIDERGON:3-D TOPOLOGY OF DELAY OPTIMIZATION FOR NETWORKS-ON-CHIP 被引量:2
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作者 周磊 吴宁 葛芬 《Transactions of Nanjing University of Aeronautics and Astronautics》 EI 2011年第4期372-378,共7页
A 3-D topology architeeture based on Spidergon and its generation method are proposed. Aiming at establishing relationships between the topology architecture and the latency, the 3-D topology latency model based on pr... A 3-D topology architeeture based on Spidergon and its generation method are proposed. Aiming at establishing relationships between the topology architecture and the latency, the 3-D topology latency model based on prototype is proposed, and then the optimization topology structure with minimum latency is determined based on it. Meanwhile, in accordance with the structure, the adaptive routing algorithm is designed. The algorithm sets longitudinal direction priority to adaptively searching the equivalent minimum path between the source nodes and the destination nodes in order to increase network throughput. Simulation shows that in case of approximate saturation network, compared with the same scale 3-D mesh structure, 3-D Spidergon has 17% less latency and 16.7% more network throughput. 展开更多
关键词 network-on-chip(NoC) TOPOLOGY spidergon routing algorithm
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