In the 9 December 2024 issue of Nature[1],a team of Google engineers reported breakthrough results using“Willow”,their lat-est quantum computing chip(Fig.1).By meeting a milestone“below threshold”reduction in the ...In the 9 December 2024 issue of Nature[1],a team of Google engineers reported breakthrough results using“Willow”,their lat-est quantum computing chip(Fig.1).By meeting a milestone“below threshold”reduction in the rate of errors that plague super-conducting circuit-based quantum computing systems(Fig.2),the work moves the field another step towards its promised super-charged applications,albeit likely still many years away.Areas expected to benefit from quantum computing include,among others,drug discovery,materials science,finance,cybersecurity,and machine learning.展开更多
Robotic computing systems play an important role in enabling intelligent robotic tasks through intelligent algo-rithms and supporting hardware.In recent years,the evolution of robotic algorithms indicates a roadmap fr...Robotic computing systems play an important role in enabling intelligent robotic tasks through intelligent algo-rithms and supporting hardware.In recent years,the evolution of robotic algorithms indicates a roadmap from traditional robotics to hierarchical and end-to-end models.This algorithmic advancement poses a critical challenge in achieving balanced system-wide performance.Therefore,algorithm-hardware co-design has emerged as the primary methodology,which ana-lyzes algorithm behaviors on hardware to identify common computational properties.These properties can motivate algo-rithm optimization to reduce computational complexity and hardware innovation from architecture to circuit for high performance and high energy efficiency.We then reviewed recent works on robotic and embodied AI algorithms and computing hard-ware to demonstrate this algorithm-hardware co-design methodology.In the end,we discuss future research opportunities by answering two questions:(1)how to adapt the computing platforms to the rapid evolution of embodied AI algorithms,and(2)how to transform the potential of emerging hardware innovations into end-to-end inference improvements.展开更多
This paper introduces a new datapath architecture for reconfigurable processors. The proposed datapath is based on Network-on-Chip approach and facilitates tight coupling of all functional units. Reconfigurable functi...This paper introduces a new datapath architecture for reconfigurable processors. The proposed datapath is based on Network-on-Chip approach and facilitates tight coupling of all functional units. Reconfigurable functional elements can be dynamically allocated for application specific optimizations, enabling polymorphic computing. Using a modified network simulator, performance of several NoC topologies and parameters are investigated with standard benchmark programs, including fine grain and coarse grain computations. Simulation results highlight the flexibility and scalability of the proposed polymorphic NoC processor for a wide range of application domains.展开更多
A method for determination of tool-chip contact length is theoreticallypresented in orthogonal metal machining. By using computer simulation and based on the analyses ofthe elastro-plastic deformation with lagrangian ...A method for determination of tool-chip contact length is theoreticallypresented in orthogonal metal machining. By using computer simulation and based on the analyses ofthe elastro-plastic deformation with lagrangian finite element method in the deformation zone, theaccumulated representative length of the low layer, the tool-chip contact length of the chipcontacting the tool rake are calculated, experimental studies are also carried out with 0.2 percentcarbon steel. It is shown that the tool-chip contact lengths obtained from computer simulation havea good agreement with those of measured values.展开更多
Developed a new program structure using in single chip computer system, which based on multitasking mechanism. Discussed the specific method for realization of the new structure. The applied sample is also provided.
In order to cool computer chip efficiently with the least noise, a single phase water-cooling radiator for computer chip driven by piezoelectric pump with two parallel-connection chambers is developed. The structure a...In order to cool computer chip efficiently with the least noise, a single phase water-cooling radiator for computer chip driven by piezoelectric pump with two parallel-connection chambers is developed. The structure and work principle of this radiator is described. Material, processing method and design principles of whole radiator are also explained. Finite element analysis （FEA） software, ANSYS, is used to simulate the heat distribution in the radiator. Testing equipments for water-cooling radiator are also listed. By experimental tests, influences of flowrate inside the cooling system and fan on chip cooling are explicated. This water-cooling radiator is proved more efficient than current air-cooling radiator with comparison experiments. During cooling the heater which simulates the working of computer chip with different power, the water-cooling radiator needs shorter time to reach lower steady temperatures than current air-cooling radiator.展开更多
This paper describes a 2D/3D vision chip with integrated sensing and processing capabilities.The 2D/3D vision chip architecture includes a 2D/3D image sensor and a programmable visual processor.In this architecture,we...This paper describes a 2D/3D vision chip with integrated sensing and processing capabilities.The 2D/3D vision chip architecture includes a 2D/3D image sensor and a programmable visual processor.In this architecture,we design a novel on-chip processing flow with die-to-die image transmission and low-latency fixed-point image processing.The vision chip achieves real-time end-to-end processing of convolutional neural networks(CNNs)and conventional image processing algo-rithms.Furthermore,an end-to-end 2D/3D vision system is built to exhibit the capacity of the vision chip.The vision system achieves real-timing applications under 2D and 3D scenes,such as human face detection(processing delay 10.2 ms)and depth map reconstruction(processing delay 4.1 ms).The frame rate of image acquisition,image process,and result display is larger than 30 fps.展开更多
We provide an overview of quantum photonic network on chip. We begin from the discussion of the pros and cons of several material platforms for engineering quantum photonic chips. Then we introduce and analyze the bas...We provide an overview of quantum photonic network on chip. We begin from the discussion of the pros and cons of several material platforms for engineering quantum photonic chips. Then we introduce and analyze the basic building blocks and functional units of quantum photonic integrated circuits. In the main part of this review, we focus on the generation and manipulation of quantum states of light on chip and are particularly interested in some applications of advanced integrated circuits with different functionalities for quantum information processing, including quantum communication, quantum computing, and quantum simulation. We emphasize that developing fully integrated quantum photonic chip which contains sources of quantum light, integrate circuits, modulators, quantum storage, and detectors are promising approaches for future quantum photonic technologies. Recent achievements in the large scale photonic chips for linear optical computing are also included. Finally, we illustrate the challenges toward high performance quantum information processing devices and conclude with promising perspectives in this field.展开更多
Spiking neural networks(SNNs)utilize brain-like spatiotemporal spike encoding for simulating brain functions.Photonic SNN offers an ultrahigh speed and power efficiency platform for implementing high-performance neuro...Spiking neural networks(SNNs)utilize brain-like spatiotemporal spike encoding for simulating brain functions.Photonic SNN offers an ultrahigh speed and power efficiency platform for implementing high-performance neuromorphic computing.Here,we proposed a multi-synaptic photonic SNN,combining the modified remote supervised learning with delayweight co-training to achieve pattern classification.The impact of multi-synaptic connections and the robustness of the network were investigated through numerical simulations.In addition,the collaborative computing of algorithm and hardware was demonstrated based on a fabricated integrated distributed feedback laser with a saturable absorber(DFB-SA),where 10 different noisy digital patterns were successfully classified.A functional photonic SNN that far exceeds the scale limit of hardware integration was achieved based on time-division multiplexing,demonstrating the capability of hardware-algorithm co-computation.展开更多
It is still challenging to fully integrate computing in memory chip as edge learning devices.In recent work published on Science,a fully-integrated chip based on neuromorphic memristors was developed for edge learning...It is still challenging to fully integrate computing in memory chip as edge learning devices.In recent work published on Science,a fully-integrated chip based on neuromorphic memristors was developed for edge learning as artificial neural networks with functionality of synapses,dendrites,and somas.A crossbar-array memristor chip facilitated edge learning including hardware realization,learning algorithm,and cycle-parallel sign-and threshold-based learning(STELLAR)scheme.The motion control and demonstration platforms were executed to improve the edge learning ability for adapting to new scenarios.展开更多
Concentration gradient and fluid shear stress(FSS)for cell microenvironment were investigated through microfluidic technology.The Darcy–Weisbach equation combined with computational fluid dynamics modeling was exploi...Concentration gradient and fluid shear stress(FSS)for cell microenvironment were investigated through microfluidic technology.The Darcy–Weisbach equation combined with computational fluid dynamics modeling was exploited to design the microfluidic chip,and the FSS distribution on the cell model with varying micro-channels(triangular,conical,and elliptical).The diffusion with the incompressible laminar flow model by solving the time-dependent diffusion–convection equation was applied to simulate the gradient profiles of concentration in the micro-channels.For the study of single cell in-depth,the FSS was investigated by the usage of polystyrene particles and the concentration diffusion distribution was studied by the usage of different colors of dyes.A successful agreement between model simulations and experimental data was obtained.Finally,based on the established method,the communication between individual cells was envisaged and modeled.The developed method provides valuable insights and allows to continuously improve the design of microfluidic devices for the study of single cell,the occurrence and development of tumors,and therapeutic applications.展开更多
This paper presents the design,optimization and fabrication of an EHD air pump intended for high-power electronic chip cooling applications.Suitable high-voltage electrode configurations were selected and studied,in t...This paper presents the design,optimization and fabrication of an EHD air pump intended for high-power electronic chip cooling applications.Suitable high-voltage electrode configurations were selected and studied,in terms of the characteristics of the generated electric field,which play an important role in ionic wind flow.For this purpose,dedicated software is used to implement finite element analysis.Critical design parameters,such as the electric field intensity,wind velocity,current flow and power consumption are investigated.Two different laboratory prototypes are fabricated and their performances experimentally assessed.This procedure leads to the fabrication of a final prototype,which is then tested as a replacement of a typical fan for cooling a high power density electronic chip.To assist towards that end,an experimental thermal testing setup is designed and constructed to simulate the size of a personal computer’s CPU core of variable power.The parametric study leads to the fabrication of experimental single-stage EHD pumps,the optimal design of which is capable of delivering an air flow of 51 CFM with an operating voltage of 10.5 kV.Finally,the theoretical and experimental results are evaluated and potential applications are proposed.展开更多
A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarith...A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.展开更多
文摘In the 9 December 2024 issue of Nature[1],a team of Google engineers reported breakthrough results using“Willow”,their lat-est quantum computing chip(Fig.1).By meeting a milestone“below threshold”reduction in the rate of errors that plague super-conducting circuit-based quantum computing systems(Fig.2),the work moves the field another step towards its promised super-charged applications,albeit likely still many years away.Areas expected to benefit from quantum computing include,among others,drug discovery,materials science,finance,cybersecurity,and machine learning.
基金supported in part by NSFC under Grant 62422407in part by RGC under Grant 26204424in part by ACCESS–AI Chip Center for Emerging Smart Systems, sponsored by the Inno HK initiative of the Innovation and Technology Commission of the Hong Kong Special Administrative Region Government
文摘Robotic computing systems play an important role in enabling intelligent robotic tasks through intelligent algo-rithms and supporting hardware.In recent years,the evolution of robotic algorithms indicates a roadmap from traditional robotics to hierarchical and end-to-end models.This algorithmic advancement poses a critical challenge in achieving balanced system-wide performance.Therefore,algorithm-hardware co-design has emerged as the primary methodology,which ana-lyzes algorithm behaviors on hardware to identify common computational properties.These properties can motivate algo-rithm optimization to reduce computational complexity and hardware innovation from architecture to circuit for high performance and high energy efficiency.We then reviewed recent works on robotic and embodied AI algorithms and computing hard-ware to demonstrate this algorithm-hardware co-design methodology.In the end,we discuss future research opportunities by answering two questions:(1)how to adapt the computing platforms to the rapid evolution of embodied AI algorithms,and(2)how to transform the potential of emerging hardware innovations into end-to-end inference improvements.
文摘This paper introduces a new datapath architecture for reconfigurable processors. The proposed datapath is based on Network-on-Chip approach and facilitates tight coupling of all functional units. Reconfigurable functional elements can be dynamically allocated for application specific optimizations, enabling polymorphic computing. Using a modified network simulator, performance of several NoC topologies and parameters are investigated with standard benchmark programs, including fine grain and coarse grain computations. Simulation results highlight the flexibility and scalability of the proposed polymorphic NoC processor for a wide range of application domains.
基金This project is supported by Provincial Natural Science Foundation of Heilongjiang(No.A9809).
文摘A method for determination of tool-chip contact length is theoreticallypresented in orthogonal metal machining. By using computer simulation and based on the analyses ofthe elastro-plastic deformation with lagrangian finite element method in the deformation zone, theaccumulated representative length of the low layer, the tool-chip contact length of the chipcontacting the tool rake are calculated, experimental studies are also carried out with 0.2 percentcarbon steel. It is shown that the tool-chip contact lengths obtained from computer simulation havea good agreement with those of measured values.
文摘Developed a new program structure using in single chip computer system, which based on multitasking mechanism. Discussed the specific method for realization of the new structure. The applied sample is also provided.
基金This project is supported by National Hi-tech Research and Development Program of China (863 Program, No. 2002AA404250)National Natural Science Foundation of China (No. 50575093).
文摘In order to cool computer chip efficiently with the least noise, a single phase water-cooling radiator for computer chip driven by piezoelectric pump with two parallel-connection chambers is developed. The structure and work principle of this radiator is described. Material, processing method and design principles of whole radiator are also explained. Finite element analysis （FEA） software, ANSYS, is used to simulate the heat distribution in the radiator. Testing equipments for water-cooling radiator are also listed. By experimental tests, influences of flowrate inside the cooling system and fan on chip cooling are explicated. This water-cooling radiator is proved more efficient than current air-cooling radiator with comparison experiments. During cooling the heater which simulates the working of computer chip with different power, the water-cooling radiator needs shorter time to reach lower steady temperatures than current air-cooling radiator.
基金supported in part by the National Key Research and Development Program of China(Grant No.2019YFB2204300)in part by the National Natural Science Foundation of China(Grant Nos.62334008 and 62274154)in part by the Key Program of National Natural Science Foundation of China(Grant No.62134004).
文摘This paper describes a 2D/3D vision chip with integrated sensing and processing capabilities.The 2D/3D vision chip architecture includes a 2D/3D image sensor and a programmable visual processor.In this architecture,we design a novel on-chip processing flow with die-to-die image transmission and low-latency fixed-point image processing.The vision chip achieves real-time end-to-end processing of convolutional neural networks(CNNs)and conventional image processing algo-rithms.Furthermore,an end-to-end 2D/3D vision system is built to exhibit the capacity of the vision chip.The vision system achieves real-timing applications under 2D and 3D scenes,such as human face detection(processing delay 10.2 ms)and depth map reconstruction(processing delay 4.1 ms).The frame rate of image acquisition,image process,and result display is larger than 30 fps.
基金Project supported by the National Key Research and Development Program of China(Grant No.2017YFA0303700)the National Natural Science Foundation of China(Grant Nos.61632021,11621091,11627810,and 11690031)
文摘We provide an overview of quantum photonic network on chip. We begin from the discussion of the pros and cons of several material platforms for engineering quantum photonic chips. Then we introduce and analyze the basic building blocks and functional units of quantum photonic integrated circuits. In the main part of this review, we focus on the generation and manipulation of quantum states of light on chip and are particularly interested in some applications of advanced integrated circuits with different functionalities for quantum information processing, including quantum communication, quantum computing, and quantum simulation. We emphasize that developing fully integrated quantum photonic chip which contains sources of quantum light, integrate circuits, modulators, quantum storage, and detectors are promising approaches for future quantum photonic technologies. Recent achievements in the large scale photonic chips for linear optical computing are also included. Finally, we illustrate the challenges toward high performance quantum information processing devices and conclude with promising perspectives in this field.
基金supports from the National Key Research and Development Program of China (Nos.2021YFB2801900,2021YFB2801901,2021YFB2801902,2021YFB2801903,2021YFB2801904)the National Outstanding Youth Science Fund Project of National Natural Science Foundation of China (No.62022062)+1 种基金the National Natural Science Foundation of China (No.61974177)the Fundamental Research Funds for the Central Universities (No.QTZX23041).
文摘Spiking neural networks(SNNs)utilize brain-like spatiotemporal spike encoding for simulating brain functions.Photonic SNN offers an ultrahigh speed and power efficiency platform for implementing high-performance neuromorphic computing.Here,we proposed a multi-synaptic photonic SNN,combining the modified remote supervised learning with delayweight co-training to achieve pattern classification.The impact of multi-synaptic connections and the robustness of the network were investigated through numerical simulations.In addition,the collaborative computing of algorithm and hardware was demonstrated based on a fabricated integrated distributed feedback laser with a saturable absorber(DFB-SA),where 10 different noisy digital patterns were successfully classified.A functional photonic SNN that far exceeds the scale limit of hardware integration was achieved based on time-division multiplexing,demonstrating the capability of hardware-algorithm co-computation.
基金funding support from the National Natural Science Foundation of China(52172205).
文摘It is still challenging to fully integrate computing in memory chip as edge learning devices.In recent work published on Science,a fully-integrated chip based on neuromorphic memristors was developed for edge learning as artificial neural networks with functionality of synapses,dendrites,and somas.A crossbar-array memristor chip facilitated edge learning including hardware realization,learning algorithm,and cycle-parallel sign-and threshold-based learning(STELLAR)scheme.The motion control and demonstration platforms were executed to improve the edge learning ability for adapting to new scenarios.
基金National Natural Science Foundation of China(No.21804045)Fujian Provincial Department of Science and Technology(No.2019I0014)Promotion Program for Young and Middle-aged Teachers in Science and Technology Research of Huaqiao University(No.ZQN-PY612)。
文摘Concentration gradient and fluid shear stress(FSS)for cell microenvironment were investigated through microfluidic technology.The Darcy–Weisbach equation combined with computational fluid dynamics modeling was exploited to design the microfluidic chip,and the FSS distribution on the cell model with varying micro-channels(triangular,conical,and elliptical).The diffusion with the incompressible laminar flow model by solving the time-dependent diffusion–convection equation was applied to simulate the gradient profiles of concentration in the micro-channels.For the study of single cell in-depth,the FSS was investigated by the usage of polystyrene particles and the concentration diffusion distribution was studied by the usage of different colors of dyes.A successful agreement between model simulations and experimental data was obtained.Finally,based on the established method,the communication between individual cells was envisaged and modeled.The developed method provides valuable insights and allows to continuously improve the design of microfluidic devices for the study of single cell,the occurrence and development of tumors,and therapeutic applications.
文摘This paper presents the design,optimization and fabrication of an EHD air pump intended for high-power electronic chip cooling applications.Suitable high-voltage electrode configurations were selected and studied,in terms of the characteristics of the generated electric field,which play an important role in ionic wind flow.For this purpose,dedicated software is used to implement finite element analysis.Critical design parameters,such as the electric field intensity,wind velocity,current flow and power consumption are investigated.Two different laboratory prototypes are fabricated and their performances experimentally assessed.This procedure leads to the fabrication of a final prototype,which is then tested as a replacement of a typical fan for cooling a high power density electronic chip.To assist towards that end,an experimental thermal testing setup is designed and constructed to simulate the size of a personal computer’s CPU core of variable power.The parametric study leads to the fabrication of experimental single-stage EHD pumps,the optimal design of which is capable of delivering an air flow of 51 CFM with an operating voltage of 10.5 kV.Finally,the theoretical and experimental results are evaluated and potential applications are proposed.
文摘A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.
