The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage...The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage-controlled tunnel barrier is the device transport physics. The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with underlap. The physics behind this behavior is the modulation of a tunnel barrier with underlap. The underlap primarily affects the tunneling component of drain current. About 50% contribution to the gate capacitance comes from the fringing electric fields emanating from the gate metal to the source and drain. The gate capacitance reduces with underlap, which should reduce the intrinsic switching delay and increase the intrinsic cut-off frequency. However, both the on current and the transconductance reduce with underlap, and the consequence is the increase of delay and the reduction of cut-off frequency.展开更多
This paper describes the performance of AIGaN/GaN HEMTs with 2.4μm source-drain spacing. So far these are the smallest source-drain spacing AIGaN/GaN HEMTs which have been implemented with a domestic wafer and domest...This paper describes the performance of AIGaN/GaN HEMTs with 2.4μm source-drain spacing. So far these are the smallest source-drain spacing AIGaN/GaN HEMTs which have been implemented with a domestic wafer and domestic process. This paper also compares their performance with that of 4μm source-drain spacing devices. The former exhibit higher drain current, higher gain, and higher efficiency. It is especially significant that the maximum frequency of oscillation noticeably increased.展开更多
文摘The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage-controlled tunnel barrier is the device transport physics. The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with underlap. The physics behind this behavior is the modulation of a tunnel barrier with underlap. The underlap primarily affects the tunneling component of drain current. About 50% contribution to the gate capacitance comes from the fringing electric fields emanating from the gate metal to the source and drain. The gate capacitance reduces with underlap, which should reduce the intrinsic switching delay and increase the intrinsic cut-off frequency. However, both the on current and the transconductance reduce with underlap, and the consequence is the increase of delay and the reduction of cut-off frequency.
基金supported by the National Natural Science Foundation of China(No.60890191).
文摘This paper describes the performance of AIGaN/GaN HEMTs with 2.4μm source-drain spacing. So far these are the smallest source-drain spacing AIGaN/GaN HEMTs which have been implemented with a domestic wafer and domestic process. This paper also compares their performance with that of 4μm source-drain spacing devices. The former exhibit higher drain current, higher gain, and higher efficiency. It is especially significant that the maximum frequency of oscillation noticeably increased.
