Graph computing has become pervasive in many applications due to its capacity to represent complex relationships among different objects in the big data era.However,general-purpose architectures are computationally in...Graph computing has become pervasive in many applications due to its capacity to represent complex relationships among different objects in the big data era.However,general-purpose architectures are computationally inefficient for graph algorithms,and dedicated architectures can provide high efficiency,but lack flexibility.To address these challenges,this paper proposes ParaGraph,a reduced instruction set computing-five(RISC-V)-based software-hardware co-designed graph computing accelerator that can process graph algorithms in parallel,and also establishes a performance evaluation model to assess the efficiency of co-acceleration.ParaGraph handles parallel processing of typical graph algorithms on the hardware side,while performing overall functional control on the software side with custom designed instructions.ParaGraph is verified on the XCVU440 field-programmable gate array(FPGA)board with E203,a RISC-V processor.Compared with current mainstream graph computing accelerators,ParaGraph consumes 7.94%less block RAM(BRAM)resources than ThunderGP.Its power consumption is reduced by 86.90%,24.90%,and 76.38%compared with ThunderGP,HitGraph,and GraphS,respectively.The power efficiency of connected components(CC)and degree centrality(DC)algorithms is improved by an average of 6.50 times over ThunderGP,2.51 times over HitGraph,and 3.99 times over GraphS.The software-hardware co-design acceleration performance indicators H/W.Cap for CC and DC are 13.02 and 14.02,respectively.展开更多
Software and hardware loosely coupled systems,characterized by their critical role in various high-reliability applications,require robust fault tolerance mechanisms due to their complexity and the intertwined nature ...Software and hardware loosely coupled systems,characterized by their critical role in various high-reliability applications,require robust fault tolerance mechanisms due to their complexity and the intertwined nature of software and hardware components.However,the tight integration of diverse functions within the system-wide computing environment,coupled with the unclear mechanism of fault propagation,presents significant challenges in enhancing system reliability.Modern avionics systems,as a prominent example,are also inherently software-hardware loosely coupled systems,and they face similar challenges in ensuring fault tolerance.In response to these challenges,this paper proposes a fault propagation analysis method that comprehensively considers both temporal and spatial dimensions.Through in-depth analysis of dependency,fault probability,and fault propagation capability,the paper constructs a fault propagation model for software and hardware loosely coupled systems,providing a precise description of fault information.In the spatial dimension,the efficiency of fault propagation analysis is enhanced using the ant colony algorithm,while in the temporal dimension,task modeling is performed using the directed acyclic graph(DAG)model to improve the adaptability of fault propagation methods to real-time task requirements.The experimental results validate the effectiveness and efficiency of the proposed fault propagation method,demonstrating that the temporal dimension of fault propagation can effectively complement the shortcomings of spatial dimension fault propagation in meeting real-time task requirements.展开更多
基金Supported by the National Key R&D Program of China(No.2022ZD0119001)the National Natural Science Foundation of China(No.61834005)+1 种基金the Shaanxi Province Key R&D Plan(No.2022GY-027,2021GY-029)the Key Scientific Research Project of Shaanxi Department of Education(No.22JY060).
文摘Graph computing has become pervasive in many applications due to its capacity to represent complex relationships among different objects in the big data era.However,general-purpose architectures are computationally inefficient for graph algorithms,and dedicated architectures can provide high efficiency,but lack flexibility.To address these challenges,this paper proposes ParaGraph,a reduced instruction set computing-five(RISC-V)-based software-hardware co-designed graph computing accelerator that can process graph algorithms in parallel,and also establishes a performance evaluation model to assess the efficiency of co-acceleration.ParaGraph handles parallel processing of typical graph algorithms on the hardware side,while performing overall functional control on the software side with custom designed instructions.ParaGraph is verified on the XCVU440 field-programmable gate array(FPGA)board with E203,a RISC-V processor.Compared with current mainstream graph computing accelerators,ParaGraph consumes 7.94%less block RAM(BRAM)resources than ThunderGP.Its power consumption is reduced by 86.90%,24.90%,and 76.38%compared with ThunderGP,HitGraph,and GraphS,respectively.The power efficiency of connected components(CC)and degree centrality(DC)algorithms is improved by an average of 6.50 times over ThunderGP,2.51 times over HitGraph,and 3.99 times over GraphS.The software-hardware co-design acceleration performance indicators H/W.Cap for CC and DC are 13.02 and 14.02,respectively.
文摘Software and hardware loosely coupled systems,characterized by their critical role in various high-reliability applications,require robust fault tolerance mechanisms due to their complexity and the intertwined nature of software and hardware components.However,the tight integration of diverse functions within the system-wide computing environment,coupled with the unclear mechanism of fault propagation,presents significant challenges in enhancing system reliability.Modern avionics systems,as a prominent example,are also inherently software-hardware loosely coupled systems,and they face similar challenges in ensuring fault tolerance.In response to these challenges,this paper proposes a fault propagation analysis method that comprehensively considers both temporal and spatial dimensions.Through in-depth analysis of dependency,fault probability,and fault propagation capability,the paper constructs a fault propagation model for software and hardware loosely coupled systems,providing a precise description of fault information.In the spatial dimension,the efficiency of fault propagation analysis is enhanced using the ant colony algorithm,while in the temporal dimension,task modeling is performed using the directed acyclic graph(DAG)model to improve the adaptability of fault propagation methods to real-time task requirements.The experimental results validate the effectiveness and efficiency of the proposed fault propagation method,demonstrating that the temporal dimension of fault propagation can effectively complement the shortcomings of spatial dimension fault propagation in meeting real-time task requirements.
