The properties of the paths in an ROBDD representation of a Boolean function are presented and proved in the present paper, and the applications of ROBDD in calculating signal probability are also discussed. By this m...The properties of the paths in an ROBDD representation of a Boolean function are presented and proved in the present paper, and the applications of ROBDD in calculating signal probability are also discussed. By this method, the troublesome calculation of the correlation among the nodes, which is caused by the re-convergent fan-out in digital system, can be avoided and power estimation can be faster than simulation-based method in [1].展开更多
By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failu...By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failure probability of the gate,first,the first reconvergent fan-ins corresponding to the reconvergent fan-outs were identified to locate the important signal correlation nodes based on the principle of homologous signal convergence.Secondly,the reconvergent fan-in nodes of the multiple reconverging structure in the circuit were identified by the sensitization path to determine the interference sources to the signal probability calculation.Then,the weighted signal probability was calculated by combining the weighted average approach to correct the signal probability.Finally,the reconvergent fan-out was quantified by the mixed-calculation strategy of signal probability to reduce the impact of multiple reconvergent fan-outs on the accuracy.Simulation results on ISCAS85 benchmarks circuits show that the proposed method has approximate linear time-space consumption with the increase in the number of the gate,and its accuracy is 4.2%higher than that of the IWAA.展开更多
Addressing the issue of low pulse identification rates for low probability of intercept(LPI)radar signals under low signal-to-noise ratio(SNR)conditions,this paper aims to investigate a new method in the field of deep...Addressing the issue of low pulse identification rates for low probability of intercept(LPI)radar signals under low signal-to-noise ratio(SNR)conditions,this paper aims to investigate a new method in the field of deep learning to recognize modulation types of LPI radar signals efficiently.A novel algorithm combining dual efficient network(DEN)and non-local means(NLM)denoising was proposed for the identification and selection of LPI radar signals.Time-domain signals for 12 radar modulation types were simulated,adding Gaussian white noise at various SNRs to replicate complex electronic countermeasure scenarios.On this basis,the noisy radar signals undergo Choi-Williams distribution(CWD)time-frequency transformation,converting the signals into two-dimensional(2D)time-frequency images(TFIs).The TFIs are then denoised using the NLM algorithm.Finally,the denoised data is fed into the designed DEN for training and testing,with the selection results output through a softmax classifier.Simulation results demonstrate that at an SNR of-8 dB,the algorithm can achieve a recognition accuracy of 97.22%for LPI radar signals,exhibiting excellent performance under low SNR conditions.Comparative demonstrations prove that the DEN has good robustness and generalization performance under conditions of small sample sizes.This research provides a novel and effective solution for further improving the accuracy of identification and selection of LPI radar signals.展开更多
Leakage current of CMOS circuit increases dramatically with the technologyscaling down and has become a critical issue of high performance system. Subthreshold, gate andreverse biased junction band-to-band tunneling (...Leakage current of CMOS circuit increases dramatically with the technologyscaling down and has become a critical issue of high performance system. Subthreshold, gate andreverse biased junction band-to-band tunneling (BTBT) leakages are considered three maindeterminants of total leakage current. Up to now, how to accurately estimate leakage current oflarge-scale circuits within endurable time remains unsolved, even though accurate leakage modelshave been widely discussed. In this paper, the authors first dip into the stack effect of CMOStechnology and propose a new simple gate-level leakage current model. Then, a table-lookup basedtotal leakage current simulator is built up according to the model. To validate the simulator,accurate leakage current is simulated at circuit level using popular simulator HSPICE forcomparison. Some further studies such as maximum leakage current estimation, minimum leakage currentgeneration and a high-level average leakage current macromodel are introduced in detail.Experiments on ISCAS85 and ISCAS89 benchmarks demonstrate that the two proposed leakage currentestimation methods are very accurate and efficient.展开更多
In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relatio...In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relation to the signal on that node, and it also depends on signals on its neighbor nodes through coupling capacitors. Thus, for their limitation in dealing with ca-pacitively coupled nets, past jobs on power estimation are facing rigorous challenges and need to be ameliorated. This paper proposes and proves a simple and fast approach to predicting dynamic power dissipation of coupled interconnect networks: a coupling capacitor in dynamic CMOS logic circuits is decoupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor, and the whole circuit after mapping, consuming the same power as the original one, could be easily managed by generally-used gate-level power estimation tools. This paper also investigates the correlation coefficient method (CCM). Given the signal probabilities and the correlation coefficients between signals, the dynamic power of interconnect networks can be calculated by using CCM. It can be proved that the decoupling method and CCM draw identical results, that is to say, the decoupling method implicitly preserves correlation properties between signals and there is no accuracy loss in the decoupling process. Moreover, it is addressed that the coupling capacitors in static CMOS circuits could be decoupled and mapped into an equivalent cell containing a more complicated logic block, and the power can be obtained by the probability method for dynamic CMOS logic circuits.展开更多
文摘The properties of the paths in an ROBDD representation of a Boolean function are presented and proved in the present paper, and the applications of ROBDD in calculating signal probability are also discussed. By this method, the troublesome calculation of the correlation among the nodes, which is caused by the re-convergent fan-out in digital system, can be avoided and power estimation can be faster than simulation-based method in [1].
基金The National Natural Science Foundation of China(No.61502422)the Natural Science Foundation of Zhejiang Province(No.LY18F020028,LQ15F020006)the Natural Science Foundation of Zhejiang University of Technology(No.2014XY007)
文摘By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failure probability of the gate,first,the first reconvergent fan-ins corresponding to the reconvergent fan-outs were identified to locate the important signal correlation nodes based on the principle of homologous signal convergence.Secondly,the reconvergent fan-in nodes of the multiple reconverging structure in the circuit were identified by the sensitization path to determine the interference sources to the signal probability calculation.Then,the weighted signal probability was calculated by combining the weighted average approach to correct the signal probability.Finally,the reconvergent fan-out was quantified by the mixed-calculation strategy of signal probability to reduce the impact of multiple reconvergent fan-outs on the accuracy.Simulation results on ISCAS85 benchmarks circuits show that the proposed method has approximate linear time-space consumption with the increase in the number of the gate,and its accuracy is 4.2%higher than that of the IWAA.
文摘Addressing the issue of low pulse identification rates for low probability of intercept(LPI)radar signals under low signal-to-noise ratio(SNR)conditions,this paper aims to investigate a new method in the field of deep learning to recognize modulation types of LPI radar signals efficiently.A novel algorithm combining dual efficient network(DEN)and non-local means(NLM)denoising was proposed for the identification and selection of LPI radar signals.Time-domain signals for 12 radar modulation types were simulated,adding Gaussian white noise at various SNRs to replicate complex electronic countermeasure scenarios.On this basis,the noisy radar signals undergo Choi-Williams distribution(CWD)time-frequency transformation,converting the signals into two-dimensional(2D)time-frequency images(TFIs).The TFIs are then denoised using the NLM algorithm.Finally,the denoised data is fed into the designed DEN for training and testing,with the selection results output through a softmax classifier.Simulation results demonstrate that at an SNR of-8 dB,the algorithm can achieve a recognition accuracy of 97.22%for LPI radar signals,exhibiting excellent performance under low SNR conditions.Comparative demonstrations prove that the DEN has good robustness and generalization performance under conditions of small sample sizes.This research provides a novel and effective solution for further improving the accuracy of identification and selection of LPI radar signals.
文摘Leakage current of CMOS circuit increases dramatically with the technologyscaling down and has become a critical issue of high performance system. Subthreshold, gate andreverse biased junction band-to-band tunneling (BTBT) leakages are considered three maindeterminants of total leakage current. Up to now, how to accurately estimate leakage current oflarge-scale circuits within endurable time remains unsolved, even though accurate leakage modelshave been widely discussed. In this paper, the authors first dip into the stack effect of CMOStechnology and propose a new simple gate-level leakage current model. Then, a table-lookup basedtotal leakage current simulator is built up according to the model. To validate the simulator,accurate leakage current is simulated at circuit level using popular simulator HSPICE forcomparison. Some further studies such as maximum leakage current estimation, minimum leakage currentgeneration and a high-level average leakage current macromodel are introduced in detail.Experiments on ISCAS85 and ISCAS89 benchmarks demonstrate that the two proposed leakage currentestimation methods are very accurate and efficient.
基金This work was supported by the National Natural Science Foundation of China (Grant No. 60025101) and in part by the National Fundamental Research Program under contract G1999032903.
文摘In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relation to the signal on that node, and it also depends on signals on its neighbor nodes through coupling capacitors. Thus, for their limitation in dealing with ca-pacitively coupled nets, past jobs on power estimation are facing rigorous challenges and need to be ameliorated. This paper proposes and proves a simple and fast approach to predicting dynamic power dissipation of coupled interconnect networks: a coupling capacitor in dynamic CMOS logic circuits is decoupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor, and the whole circuit after mapping, consuming the same power as the original one, could be easily managed by generally-used gate-level power estimation tools. This paper also investigates the correlation coefficient method (CCM). Given the signal probabilities and the correlation coefficients between signals, the dynamic power of interconnect networks can be calculated by using CCM. It can be proved that the decoupling method and CCM draw identical results, that is to say, the decoupling method implicitly preserves correlation properties between signals and there is no accuracy loss in the decoupling process. Moreover, it is addressed that the coupling capacitors in static CMOS circuits could be decoupled and mapped into an equivalent cell containing a more complicated logic block, and the power can be obtained by the probability method for dynamic CMOS logic circuits.
