Higher-s dielectric LaLuO3, deposited by molecular beam deposition, with TiN as gate stack is integrated into high-mobility Si/SiGe/SOI quantum-well p-type metal-oxide-semiconduetor field effect transistors. Threshold...Higher-s dielectric LaLuO3, deposited by molecular beam deposition, with TiN as gate stack is integrated into high-mobility Si/SiGe/SOI quantum-well p-type metal-oxide-semiconduetor field effect transistors. Threshold voltage shift and capacitance equivalent thickness shrink are observed, resulting from oxygen scavenging effect in LaLuO3 with ti-rich TiN after high temperature annealing. The mechanism of oxygen scavenging and its potential for resistive memory applications are analyzed and discussed.展开更多
在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以...在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以提高了电路的速度和驱动能力。另外由于两种极性的 SOI MOSFET都采用 Si Ge沟道 ,就避免了只有 SOIPMOSFET采用 Si Ge沟道带来的选择性生长 Si Ge层的麻烦。采用二维工艺模拟得到了器件的结构 ,并以此结构参数进行了器件模拟。模拟结果表明 ,N沟和 P沟两种 MOSFET的驱动电流都有所增加 。展开更多
The product of the cutoff frequency and breakdown voltage （fT x BVCEo） is an important figure of merit （FOM） to characterize overall performance of heterojunction bipolar transistor （HBT）. In this paper, an appr...The product of the cutoff frequency and breakdown voltage （fT x BVCEo） is an important figure of merit （FOM） to characterize overall performance of heterojunction bipolar transistor （HBT）. In this paper, an approach to introducing a thin N＋-buried layer into N collector region in silicon-on-insulator （SOI） SiGe HBT to simultaneously improve the FOM of fT×BVCEO and thermal stability is presented by using two-dimensional （2D） numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOl structure, the effects of SOI insulation layer thickness （TBox） on fT, BVCEO, and the FOM of fT×BVCEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fw, slightly increases BVcEO to some extent, but ultimately degrades the FOM of fTXBVcEo. Although the fT, BVcEo, and the FOM of fTXBVCEO can be improved by increasing SOI insulator SiO2 layer thickness TBOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiOa layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N＋-buried layer is introduced into collector region to not only improve the FOM of fT ×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N＋-buried layer in collector region is investigated in detail. The result show that the FOM of fT xBVcEo is improved and the device temperature decreases as the N＋-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N＋-buried layer into collector region provides an effective method to improve SOI SiGe HBT overall performance.展开更多
In order to improve the electrical and frequency characteristics of SiGe heterojunction bipolar transistors (HBTs), a novel structure of SOI SiGe heterojunction bipolar transistor is designed in this work. Compared wi...In order to improve the electrical and frequency characteristics of SiGe heterojunction bipolar transistors (HBTs), a novel structure of SOI SiGe heterojunction bipolar transistor is designed in this work. Compared with traditional SOI SiGe HBT, the proposed device structure has smaller window widths of emitter and collector areas. Under the act of additional uniaxial stress induced by Si0.85Ge0.15, all the collector region, base region and emitter region are strained, which is beneficial to improve the performance of SiGe HBTs. Employing the SILVACOⓇTCAD tools, the numerical simulation results show that the maximum current gain βmax, the Earley voltage VA are achieved for 1062 and 186 V, respectively, the product of β and VA, i.e., β ×VA, is 1.975 × 105 V and, the peak cutoff frequency fT is 419 GHz when the Ge component in the base has configured to be a trapezoidal distribution. The proposed SOI SiGe HBT architecture has a 52.9% improvement in cutoff frequency fT compared to the conventional SOI SiGe HBTs.展开更多
A SiGe/Si multi-quantum wells resonant-cavity-enhanced(RCE) detector with high reflectivity bottom mirror is fabricated by a new method.The bottom mirror is deposited in the hole,which is etched from the backside of t...A SiGe/Si multi-quantum wells resonant-cavity-enhanced(RCE) detector with high reflectivity bottom mirror is fabricated by a new method.The bottom mirror is deposited in the hole,which is etched from the backside of the sample by ethylenediamine-pyrocatechol-water(EPW) solution with the buried SiO 2 layer in SOI substrate as the etching-stop layer.Reflectivity spectrum indicates that the mirror deposited in the hole has a reflectivity as high as 99% in the range of 1.2～1.5μm.The peak responsivity of the RCE detector at 1.344μm is 1.2mA/W and the full width at half maximum is 12nm.Compared with the conventional p-i-n photodetector,the responsivity of RCE detector is enhanced 8 times.展开更多
The effects of buried oxide（BOX） layer on the capacitance of SiGe heterojunction photo-transistor（HPT）,including the collector-substrate capacitance,the base-collector capacitance,and the base-emitter capacitance,...The effects of buried oxide（BOX） layer on the capacitance of SiGe heterojunction photo-transistor（HPT）,including the collector-substrate capacitance,the base-collector capacitance,and the base-emitter capacitance,are studied by using a silicon-on-insulator（SOI） substrate as compared with the devices on native Si substrates.By introducing the BOX layer into Si-based SiGe HPT,the maximum photo-characteristic frequency ft,0 p.of SO1-based SiGe HPT reaches up to 24.51 GHz,which is 1.5 times higher than the value obtained from Si-based SiGe HPT.In addition,the maximum optical cut-off frequency fβ,opt,namely its 3-dB bandwidth,reaches up to 1.13 GHz,improved by 1.18 times.However,with the increase of optical power or collector current,this improvement on the frequency characteristic from BOX layer becomes less dominant as confirmed by reducing the 3-dB bandwidth of SOI-based SiGe HPT which approaches to the 3-dB bandwidth of Si-based SiGe HPT at higher injection conditions.展开更多
The tensile strained Ge/SiGe multiple quantum wells （MQWs） grown on a silicon-on-insulator （SOI） substrate were fabricated successfully by ultra-high chemical vapor deposition. Room temperature direct band photolu...The tensile strained Ge/SiGe multiple quantum wells （MQWs） grown on a silicon-on-insulator （SOI） substrate were fabricated successfully by ultra-high chemical vapor deposition. Room temperature direct band photoluminescence from Ge quantum wells on SOI substrate is strongly modulated by Fabry-Perot cavity formed between the surface of Ge and the interface of buried SiO2. The photoluminescence peak intensity at 1.58 μm is enhanced by about 21 times compared with that from the Ge/SiGe quantum wells on Si substrate, and the full width at half maximum （FWHM） is significantly reduced. It is suggested that tensile strained Ge/SiGe multiple quantum wells are one of the promising materials for Si-based microcavity lijzht emitting devices.展开更多
基金Supported by the National Natural Science Foundation of China under Grant No 61306126
文摘Higher-s dielectric LaLuO3, deposited by molecular beam deposition, with TiN as gate stack is integrated into high-mobility Si/SiGe/SOI quantum-well p-type metal-oxide-semiconduetor field effect transistors. Threshold voltage shift and capacitance equivalent thickness shrink are observed, resulting from oxygen scavenging effect in LaLuO3 with ti-rich TiN after high temperature annealing. The mechanism of oxygen scavenging and its potential for resistive memory applications are analyzed and discussed.
文摘在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以提高了电路的速度和驱动能力。另外由于两种极性的 SOI MOSFET都采用 Si Ge沟道 ,就避免了只有 SOIPMOSFET采用 Si Ge沟道带来的选择性生长 Si Ge层的麻烦。采用二维工艺模拟得到了器件的结构 ,并以此结构参数进行了器件模拟。模拟结果表明 ,N沟和 P沟两种 MOSFET的驱动电流都有所增加 。
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61574010,60776051,61006059,and 61006044)the Beijing Municipal Natural Science Foundation,China(Grant No.4142007)the Beijing Municipal Education Committee,China(Grant No.KM200910005001)
文摘The product of the cutoff frequency and breakdown voltage （fT x BVCEo） is an important figure of merit （FOM） to characterize overall performance of heterojunction bipolar transistor （HBT）. In this paper, an approach to introducing a thin N＋-buried layer into N collector region in silicon-on-insulator （SOI） SiGe HBT to simultaneously improve the FOM of fT×BVCEO and thermal stability is presented by using two-dimensional （2D） numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOl structure, the effects of SOI insulation layer thickness （TBox） on fT, BVCEO, and the FOM of fT×BVCEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fw, slightly increases BVcEO to some extent, but ultimately degrades the FOM of fTXBVcEo. Although the fT, BVcEo, and the FOM of fTXBVCEO can be improved by increasing SOI insulator SiO2 layer thickness TBOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiOa layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N＋-buried layer is introduced into collector region to not only improve the FOM of fT ×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N＋-buried layer in collector region is investigated in detail. The result show that the FOM of fT xBVcEo is improved and the device temperature decreases as the N＋-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N＋-buried layer into collector region provides an effective method to improve SOI SiGe HBT overall performance.
文摘In order to improve the electrical and frequency characteristics of SiGe heterojunction bipolar transistors (HBTs), a novel structure of SOI SiGe heterojunction bipolar transistor is designed in this work. Compared with traditional SOI SiGe HBT, the proposed device structure has smaller window widths of emitter and collector areas. Under the act of additional uniaxial stress induced by Si0.85Ge0.15, all the collector region, base region and emitter region are strained, which is beneficial to improve the performance of SiGe HBTs. Employing the SILVACOⓇTCAD tools, the numerical simulation results show that the maximum current gain βmax, the Earley voltage VA are achieved for 1062 and 186 V, respectively, the product of β and VA, i.e., β ×VA, is 1.975 × 105 V and, the peak cutoff frequency fT is 419 GHz when the Ge component in the base has configured to be a trapezoidal distribution. The proposed SOI SiGe HBT architecture has a 52.9% improvement in cutoff frequency fT compared to the conventional SOI SiGe HBTs.
文摘A SiGe/Si multi-quantum wells resonant-cavity-enhanced(RCE) detector with high reflectivity bottom mirror is fabricated by a new method.The bottom mirror is deposited in the hole,which is etched from the backside of the sample by ethylenediamine-pyrocatechol-water(EPW) solution with the buried SiO 2 layer in SOI substrate as the etching-stop layer.Reflectivity spectrum indicates that the mirror deposited in the hole has a reflectivity as high as 99% in the range of 1.2～1.5μm.The peak responsivity of the RCE detector at 1.344μm is 1.2mA/W and the full width at half maximum is 12nm.Compared with the conventional p-i-n photodetector,the responsivity of RCE detector is enhanced 8 times.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61604106,61774012,and 61901010)the Beijing Future Chip Technology High Precision Innovation Center Research Fund,China(Grant No.KYJJ2016008)+1 种基金the Beijing Municipal Natural Science Foundation,China(Grant No.4192014)the Municipal Natural Science Foundation of Shangdong Province,China(Grant No.ZR2014FL025).
文摘The effects of buried oxide（BOX） layer on the capacitance of SiGe heterojunction photo-transistor（HPT）,including the collector-substrate capacitance,the base-collector capacitance,and the base-emitter capacitance,are studied by using a silicon-on-insulator（SOI） substrate as compared with the devices on native Si substrates.By introducing the BOX layer into Si-based SiGe HPT,the maximum photo-characteristic frequency ft,0 p.of SO1-based SiGe HPT reaches up to 24.51 GHz,which is 1.5 times higher than the value obtained from Si-based SiGe HPT.In addition,the maximum optical cut-off frequency fβ,opt,namely its 3-dB bandwidth,reaches up to 1.13 GHz,improved by 1.18 times.However,with the increase of optical power or collector current,this improvement on the frequency characteristic from BOX layer becomes less dominant as confirmed by reducing the 3-dB bandwidth of SOI-based SiGe HPT which approaches to the 3-dB bandwidth of Si-based SiGe HPT at higher injection conditions.
基金supported by the National Natural Science Foundation of China(Nos.61036003 and 61176092)the Ph.D.Programs Foundation of Ministry of Education of China(No.20110121110025)
文摘The tensile strained Ge/SiGe multiple quantum wells （MQWs） grown on a silicon-on-insulator （SOI） substrate were fabricated successfully by ultra-high chemical vapor deposition. Room temperature direct band photoluminescence from Ge quantum wells on SOI substrate is strongly modulated by Fabry-Perot cavity formed between the surface of Ge and the interface of buried SiO2. The photoluminescence peak intensity at 1.58 μm is enhanced by about 21 times compared with that from the Ge/SiGe quantum wells on Si substrate, and the full width at half maximum （FWHM） is significantly reduced. It is suggested that tensile strained Ge/SiGe multiple quantum wells are one of the promising materials for Si-based microcavity lijzht emitting devices.
