In this paper,a high-gain inductorless LNA(low-noise amplifier)compatible with multiple communication protocols from 0.1 to 5.1 GHz is proposed.A composite resistor-capacitor feedback structure is employed to achieve ...In this paper,a high-gain inductorless LNA(low-noise amplifier)compatible with multiple communication protocols from 0.1 to 5.1 GHz is proposed.A composite resistor-capacitor feedback structure is employed to achieve a wide bandwidth matching range and good gain flatness.A second stage with a Darlington pair is used to increase the overall gain of the amplifier,while the gain of the first stage is reduced to reduce the overall noise.The amplifier is based on a 0.25μm SiGe BiCMOS process,and thanks to the inductorless circuit structure,the core circuit area is only 0.03 mm^(2).Test results show that the lowest noise figure(NF)in the operating band is 1.99 dB,the power gain reaches 29.7 dB,the S_(11)and S_(22)are less than-10 dB,the S_(12)is less than-30 dB,the IIP3 is 0.81dBm,and the OP_(1dB)is 10.27 dBm.The operating current is 31.18 mA at 3.8 V supply.展开更多
An integer-N frequency synthesizer in 0.35μm SiGe BiCMOS is presented. By implementing different building blocks with different types of devices,a high purity frequency synthesizer with excellent spur and phase noise...An integer-N frequency synthesizer in 0.35μm SiGe BiCMOS is presented. By implementing different building blocks with different types of devices,a high purity frequency synthesizer with excellent spur and phase noise performance has been realized. All the building blocks are implemented with differential topology except for the off-chip loop filter. To further reduce the phase noise,bonding wires are used to form the resonator in the LC-VCO. The frequency synthesizer operates from 2.39 to 2.72GHz with output power of about 0dBm. The measured closed-loop phase noise is - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from the carrier. The power level of the reference spur is less than - 72dBc. With a 3V power supply, the whole chip including the output buffers consumes 60mA.展开更多
This paper introduces a 2.5GHz low phase-noise cross-coupled LC-VCO realized in 0.35μm SiGe BiCMOS technology. The conventional definition of a VCO operating regime is revised from a new perspective. Analysis shows t...This paper introduces a 2.5GHz low phase-noise cross-coupled LC-VCO realized in 0.35μm SiGe BiCMOS technology. The conventional definition of a VCO operating regime is revised from a new perspective. Analysis shows the importance of inductance and bias current selection for oscillator phase noise optimization. Differences between CMOS and BJT VCO design strategy are then analyzed and the conclusions are summarized. In this implementation, bonding wires form the resonator to improve the phase noise performance. The VCO is then integrated with other components to form a PLL frequency synthesizer with a loop bandwidth of 30kHz. Measurement shows a phase noise of - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from a 2.5GHz carrier. At a supply voltage of 3V, the VCO core consumes 8mA. To our knowledge,this is the first differential cross-coupled VCO in SiGe BiCMOS technology in China.展开更多
基金funded by the Science,Technology and Innovation Commission of Shenzhen Municipality(JCYJ20220818101001003)。
文摘In this paper,a high-gain inductorless LNA(low-noise amplifier)compatible with multiple communication protocols from 0.1 to 5.1 GHz is proposed.A composite resistor-capacitor feedback structure is employed to achieve a wide bandwidth matching range and good gain flatness.A second stage with a Darlington pair is used to increase the overall gain of the amplifier,while the gain of the first stage is reduced to reduce the overall noise.The amplifier is based on a 0.25μm SiGe BiCMOS process,and thanks to the inductorless circuit structure,the core circuit area is only 0.03 mm^(2).Test results show that the lowest noise figure(NF)in the operating band is 1.99 dB,the power gain reaches 29.7 dB,the S_(11)and S_(22)are less than-10 dB,the S_(12)is less than-30 dB,the IIP3 is 0.81dBm,and the OP_(1dB)is 10.27 dBm.The operating current is 31.18 mA at 3.8 V supply.
文摘An integer-N frequency synthesizer in 0.35μm SiGe BiCMOS is presented. By implementing different building blocks with different types of devices,a high purity frequency synthesizer with excellent spur and phase noise performance has been realized. All the building blocks are implemented with differential topology except for the off-chip loop filter. To further reduce the phase noise,bonding wires are used to form the resonator in the LC-VCO. The frequency synthesizer operates from 2.39 to 2.72GHz with output power of about 0dBm. The measured closed-loop phase noise is - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from the carrier. The power level of the reference spur is less than - 72dBc. With a 3V power supply, the whole chip including the output buffers consumes 60mA.
文摘This paper introduces a 2.5GHz low phase-noise cross-coupled LC-VCO realized in 0.35μm SiGe BiCMOS technology. The conventional definition of a VCO operating regime is revised from a new perspective. Analysis shows the importance of inductance and bias current selection for oscillator phase noise optimization. Differences between CMOS and BJT VCO design strategy are then analyzed and the conclusions are summarized. In this implementation, bonding wires form the resonator to improve the phase noise performance. The VCO is then integrated with other components to form a PLL frequency synthesizer with a loop bandwidth of 30kHz. Measurement shows a phase noise of - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from a 2.5GHz carrier. At a supply voltage of 3V, the VCO core consumes 8mA. To our knowledge,this is the first differential cross-coupled VCO in SiGe BiCMOS technology in China.
