GeSi source/drain structure is purposefully adopted in SOI p MOSFET's to suppress the short channel effect (SCE).The impact of GeSi material (as source only,drain only or both source and drain) on the threshold v...GeSi source/drain structure is purposefully adopted in SOI p MOSFET's to suppress the short channel effect (SCE).The impact of GeSi material (as source only,drain only or both source and drain) on the threshold voltage rolling off and DIBL effect is thoroughly investigated,as well as the influence of the Ge concentration and silicon film thickness.The Ge concentration should be carefully chosen as a tradeoff between the driving current and SCE improvement.The detailed physics is explained.展开更多
An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented...An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.展开更多
In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along wit...In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.展开更多
Besides the common short-channel effect(SCE)of threshold voltage(V_(th))roll-off during the channel length(L)downscaling of In GaZnO(IGZO)thin-film transistors(TFTs),an opposite V_(th)roll-up was reported in this work...Besides the common short-channel effect(SCE)of threshold voltage(V_(th))roll-off during the channel length(L)downscaling of In GaZnO(IGZO)thin-film transistors(TFTs),an opposite V_(th)roll-up was reported in this work.Both roll-off and roll-up effects of Vth were comparatively investigated on IGZO transistors with varied gate insulator(GI),source/drain(S/D),and device architecture.For IGZO transistors with thinner GI,the SCE was attenuated due to the enhanced gate controllability over the variation of channel carrier concentration,while the Vth roll-up became more noteworthy.The latter was found to depend on the relative ratio of S/D series resistance(R_(SD))over channel resistance(R_(CH)),as verified on transistors with different S/D.Thus,an ideal S/D engineering with small R_(SD)but weak dopant diffusion is highly expected during the downscaling of L and GI in IGZO transistors.展开更多
This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack chan...This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.展开更多
The relentless down-scaling of electronics grands the modern integrated circuits(ICs)with the high speed,low power dissipation and low cost,fulfilling diverse demands of modern life.Whereas,with the semiconductor indu...The relentless down-scaling of electronics grands the modern integrated circuits(ICs)with the high speed,low power dissipation and low cost,fulfilling diverse demands of modern life.Whereas,with the semiconductor industry entering into sub-10 nm technology nodes,degrading device performance and increasing power consumption give rise to insurmountable roadblocks confronted by modern ICs that need to be conquered to sustain the Moore law's life.Bulk semiconductors like prevalent Si are plagued by seriously degraded carrier mobility as thickness thinning down to sub-5 nm,which is imperative to maintain sufficient gate electrostatic controllability to combat the increasingly degraded short channel effects.Nowadays,the emergence of two-dimensional(2D)materials opens up new gateway to eschew the hurdles laid in front of the scaling trend of modern IC,mainly ascribed to their ultimately atomic thickness,capability to maintain carrier mobility with thickness thinning down,dangling-bonds free surface,wide bandgaps tunability and feasibility to constitute diverse heterostructures.Blossoming breakthroughs in discrete electronic device,such as contact engineering,dielectric integration and vigorous channel-length scaling,or large circuits arrays,as boosted yields,improved variations and full-functioned processor fabrication,based on 2D materials have been achieved nowadays,facilitating 2D materials to step under the spotlight of IC industry to be treated as the most potential future successor or complementary counterpart of incumbent Si to further sustain the down-scaling of modern IC.展开更多
Based on the exact resultant solution of two-dimensional Poisson＇s equation in strained Si and Si1-xCex layer, a simple and accurate two-dimensional.analytical model including surface channel potential, surface chann...Based on the exact resultant solution of two-dimensional Poisson＇s equation in strained Si and Si1-xCex layer, a simple and accurate two-dimensional.analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator （SGOI） MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects （SCE）, the drain-induced barrier-lowering （DIBL） and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.展开更多
An SOI MOSFET with FINFET structure is simulated using a 3 D simulator. I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully investigated.SCE can be well c...An SOI MOSFET with FINFET structure is simulated using a 3 D simulator. I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully investigated.SCE can be well controlled by reducing fin height.Good performance can be achieved with thin height,so fin height is considered as a key parameter in device design.Simulation results show that FINFETs present performance superior to conventional single gate devices.展开更多
Threshold voltage (V<sub>TH</sub>) is the most evocative aspect of MOSFET operation. It is the crucial device constraint to model on-off transition characteristics. Precise V<sub>TH</sub> value...Threshold voltage (V<sub>TH</sub>) is the most evocative aspect of MOSFET operation. It is the crucial device constraint to model on-off transition characteristics. Precise V<sub>TH</sub> value of the device is extracted and evaluated by several estimation techniques. However, these assessed values of V<sub>TH</sub> diverge from the exact values due to various short channel effects (SCEs) and non-idealities present in the device. Numerous prevalent V<sub>TH</sub> extraction methods are discussed. All the results are verified by extensive 2-D TCAD simulation and confirmed through analytical results at 10-nm technology node. Aim of this research paper is to explore and present a comparative study of largely applied threshold extraction methods for bulk driven nano-MOSFETs especially at 10-nm technology node along with various sub 45-nm technology nodes. Application of the threshold extraction methods to implement noise analysis is briefly presented to infer the most appropriate extraction method at nanometer technology nodes.展开更多
DG-MOSFETs are the most widely explored device architectures for na</span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="f...DG-MOSFETs are the most widely explored device architectures for na</span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">no-scale CMOS circuit design in sub-50 nm due to the improved subthre</span></span></span><span><span><span style="font-family:""><span style="font-family:Verdana;">shold slope and the reduced leakage power compared to bulk MOSFETs. In thin-film (</span><i><span style="font-family:Verdana;">t</span><sub><span style="font-family:Verdana;">si</span></sub></i><span style="font-family:Verdana;"> < 10 nm) DG-MOS structures, charge carriers are affected</span></span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;"> by</span></span></span><span><span><span style="font-family:""> <i><span style="font-family:Verdana;">t</span><sub><span style="font-family:Verdana;">si</span></sub></i><span style="font-family:Verdana;">-</span></span></span></span><span><span><span style="font-family:""> </span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">induced quantum confinement along with the confinement caused by </span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">a </span></span></span><span><span><span style="font-family:""><span style="font-family:Verdana;">very high electric field at the interface. Therefore, quantum confinement effects on the device characteristics are also quite important and it needs to be incorpo</span><span style="font-family:Verdana;">rated along with short channel effects for nano-scale circuit design. In this</span> </span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">paper</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">, we analyze</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">d</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;"> a DG-MOSFET structure at </span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">the </span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">20 nm technology node</span></span></span><span><span><span style="font-family:""><span style="font-family:Verdana;"> incorporating quantum confinement effects and various short channel effects. The effect of physical parameter variations on performance characteristics of </span><span><span style="font-family:Verdana;">the device such as threshold voltage, subthreshold slope, </span><i><span style="font-family:Verdana;">I</span><sub><span style="font-family:Verdana;">ON</span></sub></i><span style="font-family:Verdana;"> - </span><i><span style="font-family:Verdana;">I</span><sub><span style="font-family:Verdana;">OFF</span></sub></i><span style="font-family:Verdana;"> ratio,</span></span> <i><span style="font-family:Verdana;">DIBL</span></i></span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">,</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;"> etc. has been investigated and plotted through extensive TCAD simulations. The physical parameters considered in this </span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">paper</span></span></span><span><span><span style="font-family:""><span style="font-family:Verdana;"> are operating temperature </span><span><span style="font-family:Verdana;">(</span><i><span style="font-family:Verdana;">T</span><sub><span style="font-family:Verdana;">op</span></sub></i><span style="font-family:Verdana;">), channel doping concentration (</span><i><span style="font-family:Verdana;">N</span><sub><span style="font-family:Verdana;">c</span></sub></i><span style="font-family:Verdana;">), gate oxide thickness (</span><i><span style="font-family:Verdana;">t</span><sub><span style="font-family:Verdana;">ox</span></sub></i><span style="font-family:Verdana;">) an</span></span><span style="font-family:Verdana;">d Silicon film thickness (</span><i><span style="font-family:Verdana;">t</span><sub><span style="font-family:Verdana;">si</span></sub></i><span style="font-family:Verdana;">). It </span></span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">was</span></span></span><span><span><span style="font-family:""><span style="font-family:Verdana;"> observed that quantum confinement of </span><span style="font-family:Verdana;">charge </span><span style="font-family:Verdana;">carriers significantly affect</span></span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">ed</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;"> the performance characteristics (mostly the</span></span></span><span><span><span style="font-family:""><span style="font-family:Verdana;"> subth</span><span style="font-family:Verdana;">reshold characteristics) of the device and therefore, it cannot be ignored in</span><span style="font-family:Verdana;"> the </span><span style="font-family:Verdana;">subthreshold region</span></span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">-</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">based circuit design like in many previous research</span></span></span><span><span><span style="font-family:""><span style="font-family:Verdana;"> works. </span><span><span style="font-family:Verdana;">The ATLAS</span><sup><span style="font-family:Verdana;">TM</span></sup><span style="font-family:Verdana;"> device simulator has been used in this </span></span></span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">paper</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;"> to perform simu</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">lation and parameter extraction. The TCAD analysis presented in the</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;"> manuscript can be incorporated for device modeling and device</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;"> matching. It can be used to illustrate exact device behavior and for proper device control.展开更多
This paper aims to simulate the I–V static characteristic of the enhancement-mode（E-mode） Npolar GaN metal–insulator–semiconductor field effect transistor（MISFET） with self-aligned source/drain regions.Firstly,...This paper aims to simulate the I–V static characteristic of the enhancement-mode（E-mode） Npolar GaN metal–insulator–semiconductor field effect transistor（MISFET） with self-aligned source/drain regions.Firstly, with SILVACO TCAD device simulation, the drain–source current as a function of the gate–source voltage is calculated and the dependence of the drain–source current on the drain–source voltage in the case of different gate–source voltages for the device with a 0.62 m gate length is investigated. Secondly, a comparison is made with the experimental report. Lastly, the transfer characteristic with different gate lengths and different buffer layers has been performed. The results show that the simulation is in accord with the experiment at the gate length of 0.62 m and the short channel effect becomes pronounced as gate length decreases. The E-mode will not be held below a100 nm gate length unless both transversal scaling and vertical scaling are being carried out simultaneously.展开更多
We study the characteristics of short channel double-gate(DG) junctionless(JL) FETs by device simulation. OutputⅠ-Ⅴcharacteristic degradations such as an extremely reduced channel length induced subthreshold slope i...We study the characteristics of short channel double-gate(DG) junctionless(JL) FETs by device simulation. OutputⅠ-Ⅴcharacteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed.Distributions of electron concentration,electric field and potential in the body channel region are also analyzed.Comparisons with conventional inversion-mode(IM) FETs,which can demonstrate the advantages of JL FETs,have also been performed.展开更多
Based on the exact resultant solution of two-dimensional Poisson＇s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have bee...Based on the exact resultant solution of two-dimensional Poisson＇s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor （CMOS）-based device in a nanoscale regime.展开更多
We propose a scaling theory for single gate Al In Sb/In Sb high electron mobility transistors（HEMTs） by solving the two-dimensional（2D） Poisson equation. In our model, the effective conductive path effect（ECPE） ...We propose a scaling theory for single gate Al In Sb/In Sb high electron mobility transistors（HEMTs） by solving the two-dimensional（2D） Poisson equation. In our model, the effective conductive path effect（ECPE） is taken into account to overcome the problems arising from the device scaling. The potential in the effective conducting path is developed and a simple scaling equation is derived. This equation is solved to obtain the minimum channel potential Φdeff,minand the new scaling factor α to model the subthreshold behavior of the HEMTs. The developed model minimizes the leakage current and improves the subthreshold swing degradation of the HEMTs. The results of the analytical model are verified by numerical simulation with a Sentaurus TCAD device simulator.展开更多
We preform a first-principles study of performance of 5 nm double-gated(DG)Schottky-barrier field effect transistors(SBFETs)based on two-dimensional SiC with monolayer or bilayer metallic 1T-phase MoS_(2) contacts.Bec...We preform a first-principles study of performance of 5 nm double-gated(DG)Schottky-barrier field effect transistors(SBFETs)based on two-dimensional SiC with monolayer or bilayer metallic 1T-phase MoS_(2) contacts.Because of the wide bandgap of SiC,the corresponding DG SBFETs can weaken the short channel effect.The calculated transfer characteristics also meet the standard of the high performance transistor summarized by international technology road-map for semiconductors.Moreover,the bilayer metallic 1T-phase MoS_(2) contacts in three stacking structures all can further raise the ON-state currents of DG SiC SBFETs in varying degrees.The above results are helpful and instructive for design of short channel transistors in the future.展开更多
Deep submicron partially depleted silicon on insulator （PDSOI） nMOSFETs were fabricated based on the 0.35μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences （IMECAS）. ...Deep submicron partially depleted silicon on insulator （PDSOI） nMOSFETs were fabricated based on the 0.35μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences （IMECAS）. Mechanisms determining short-channel effects （SCE） in PDSOI nMOSFETs are clarified based on experimental results of threshold voltage dependence upon gate length. The effects of body bias, drain bias, temperature and body contact on the SCE have been investigated. The SCE in SOI devices is found to be dependent on body bias, drain bias and body contact. Floating body devices show a more severe reverse short channel effect （RSCE） than devices with body contact structure. Devices with low body bias and high drain bias show a more obvious SCE.展开更多
The evolution of the traditional metal oxide semiconductor field effect transistor(MOSFET) from planar single gate devices into 3 D multiple gates has led to higher package density and high current drive.However, due ...The evolution of the traditional metal oxide semiconductor field effect transistor(MOSFET) from planar single gate devices into 3 D multiple gates has led to higher package density and high current drive.However, due to continuous scaling and as a consequent close proximity between source and drain in the nano-regime, these multigate devices have been found to suffer from performance degrading short channel effects(SCEs).In this paper, a three dimensional analytical model of a trigate MOSFET incorporating non-conventional structural techniques like silicon-on-insulator, gate and channel engineering in addition to gate oxide stack is presented.The electrostatic integrity and device capability of suppressing SCEs is investigated by deriving the potential distribution profile using the three dimensional Poisson’s equation along with suitable boundary conditions. The other device parameters like threshold voltage and subthreshold swing are produced from the surface potential model.The validity of the proposed structure is established by the close agreement among the results obtained from the analytical model and simulation results.展开更多
Metal-oxide-semiconductor field-effect transistor(MOSFET)and complementary metal-oxide-semiconductor(CMOS)circuits are the foundation of integrated circuits development and the cornerstone of information infrastructur...Metal-oxide-semiconductor field-effect transistor(MOSFET)and complementary metal-oxide-semiconductor(CMOS)circuits are the foundation of integrated circuits development and the cornerstone of information infrastructure and artificial intelligence(AI)progress[1-3].However,as the physical scale of devices continues to shrink,Moore’s Law has faced limitations,and short channel effects(SCEs)have become increasingly severe[4,5].展开更多
Due to the increase in leakage current and the serious decrease of on/off ratio caused by short channel effect and medium tunneling effect,the continued scaling of silicon transistors has become an insurmountable obst...Due to the increase in leakage current and the serious decrease of on/off ratio caused by short channel effect and medium tunneling effect,the continued scaling of silicon transistors has become an insurmountable obstacle for the semiconductor manufacturing industry moving forward.Two-dimensional(2D)semiconductor materials hold promise for achieving high speed and low-power switching characteristics under limit node size[1-10].展开更多
This paper presents an in-depth analysis of junctionless double gate vertical slit FET（JLDG VeSFET）device under process variability.It has been observed that junctionless FETs（JLDG VeSFET） are significantly less s...This paper presents an in-depth analysis of junctionless double gate vertical slit FET（JLDG VeSFET）device under process variability.It has been observed that junctionless FETs（JLDG VeSFET） are significantly less sensitive to many process parameter variations due to their inherent device structure and geometric properties.Sensitivity analysis reveals that the slit width,oxide thickness,radius of the device,gate length and channel doping concentration imperceptibly affect the device performance of JLDG VeSFET in terms of variation in threshold voltage,on current,off current and subthreshold slope（Ssub） as compared to its junction based counterpart i.e.MOSFET,because various short channel effects are well controlled in this device.The maximum variation in off current for JLDG VeSFET due to variation in different devices parameters is 5.6% whereas this variation is 38.8% for the MOS junction based device.However,variation in doping concentration in the channel region displays a small deviation in the threshold voltage and on current characteristics of the MOSFET device as compared to JL DG VeSFET.展开更多
文摘GeSi source/drain structure is purposefully adopted in SOI p MOSFET's to suppress the short channel effect (SCE).The impact of GeSi material (as source only,drain only or both source and drain) on the threshold voltage rolling off and DIBL effect is thoroughly investigated,as well as the influence of the Ge concentration and silicon film thickness.The Ge concentration should be carefully chosen as a tradeoff between the driving current and SCE improvement.The detailed physics is explained.
文摘An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.
文摘In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.
基金supported financially by National key Research and Development Program under Grant 2021YFB3600802Shenzhen Municipal Scientific Program under Grant KJZD20230923114111021。
文摘Besides the common short-channel effect(SCE)of threshold voltage(V_(th))roll-off during the channel length(L)downscaling of In GaZnO(IGZO)thin-film transistors(TFTs),an opposite V_(th)roll-up was reported in this work.Both roll-off and roll-up effects of Vth were comparatively investigated on IGZO transistors with varied gate insulator(GI),source/drain(S/D),and device architecture.For IGZO transistors with thinner GI,the SCE was attenuated due to the enhanced gate controllability over the variation of channel carrier concentration,while the Vth roll-up became more noteworthy.The latter was found to depend on the relative ratio of S/D series resistance(R_(SD))over channel resistance(R_(CH)),as verified on transistors with different S/D.Thus,an ideal S/D engineering with small R_(SD)but weak dopant diffusion is highly expected during the downscaling of L and GI in IGZO transistors.
文摘This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.
基金supported by start-up capital of Ningbo Eastern Institute of technology。
文摘The relentless down-scaling of electronics grands the modern integrated circuits(ICs)with the high speed,low power dissipation and low cost,fulfilling diverse demands of modern life.Whereas,with the semiconductor industry entering into sub-10 nm technology nodes,degrading device performance and increasing power consumption give rise to insurmountable roadblocks confronted by modern ICs that need to be conquered to sustain the Moore law's life.Bulk semiconductors like prevalent Si are plagued by seriously degraded carrier mobility as thickness thinning down to sub-5 nm,which is imperative to maintain sufficient gate electrostatic controllability to combat the increasingly degraded short channel effects.Nowadays,the emergence of two-dimensional(2D)materials opens up new gateway to eschew the hurdles laid in front of the scaling trend of modern IC,mainly ascribed to their ultimately atomic thickness,capability to maintain carrier mobility with thickness thinning down,dangling-bonds free surface,wide bandgaps tunability and feasibility to constitute diverse heterostructures.Blossoming breakthroughs in discrete electronic device,such as contact engineering,dielectric integration and vigorous channel-length scaling,or large circuits arrays,as boosted yields,improved variations and full-functioned processor fabrication,based on 2D materials have been achieved nowadays,facilitating 2D materials to step under the spotlight of IC industry to be treated as the most potential future successor or complementary counterpart of incumbent Si to further sustain the down-scaling of modern IC.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60976068 and 60936005)the Cultivation Fund of the Key Scientific and Technical Innovation Project, Ministry of Education of China (Grant No. 708083)the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 200807010010)
文摘Based on the exact resultant solution of two-dimensional Poisson＇s equation in strained Si and Si1-xCex layer, a simple and accurate two-dimensional.analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator （SGOI） MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects （SCE）, the drain-induced barrier-lowering （DIBL） and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.
文摘An SOI MOSFET with FINFET structure is simulated using a 3 D simulator. I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully investigated.SCE can be well controlled by reducing fin height.Good performance can be achieved with thin height,so fin height is considered as a key parameter in device design.Simulation results show that FINFETs present performance superior to conventional single gate devices.
文摘Threshold voltage (V<sub>TH</sub>) is the most evocative aspect of MOSFET operation. It is the crucial device constraint to model on-off transition characteristics. Precise V<sub>TH</sub> value of the device is extracted and evaluated by several estimation techniques. However, these assessed values of V<sub>TH</sub> diverge from the exact values due to various short channel effects (SCEs) and non-idealities present in the device. Numerous prevalent V<sub>TH</sub> extraction methods are discussed. All the results are verified by extensive 2-D TCAD simulation and confirmed through analytical results at 10-nm technology node. Aim of this research paper is to explore and present a comparative study of largely applied threshold extraction methods for bulk driven nano-MOSFETs especially at 10-nm technology node along with various sub 45-nm technology nodes. Application of the threshold extraction methods to implement noise analysis is briefly presented to infer the most appropriate extraction method at nanometer technology nodes.
文摘DG-MOSFETs are the most widely explored device architectures for na</span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">no-scale CMOS circuit design in sub-50 nm due to the improved subthre</span></span></span><span><span><span style="font-family:""><span style="font-family:Verdana;">shold slope and the reduced leakage power compared to bulk MOSFETs. In thin-film (</span><i><span style="font-family:Verdana;">t</span><sub><span style="font-family:Verdana;">si</span></sub></i><span style="font-family:Verdana;"> < 10 nm) DG-MOS structures, charge carriers are affected</span></span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;"> by</span></span></span><span><span><span style="font-family:""> <i><span style="font-family:Verdana;">t</span><sub><span style="font-family:Verdana;">si</span></sub></i><span style="font-family:Verdana;">-</span></span></span></span><span><span><span style="font-family:""> </span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">induced quantum confinement along with the confinement caused by </span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">a </span></span></span><span><span><span style="font-family:""><span style="font-family:Verdana;">very high electric field at the interface. Therefore, quantum confinement effects on the device characteristics are also quite important and it needs to be incorpo</span><span style="font-family:Verdana;">rated along with short channel effects for nano-scale circuit design. In this</span> </span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">paper</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">, we analyze</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">d</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;"> a DG-MOSFET structure at </span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">the </span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">20 nm technology node</span></span></span><span><span><span style="font-family:""><span style="font-family:Verdana;"> incorporating quantum confinement effects and various short channel effects. The effect of physical parameter variations on performance characteristics of </span><span><span style="font-family:Verdana;">the device such as threshold voltage, subthreshold slope, </span><i><span style="font-family:Verdana;">I</span><sub><span style="font-family:Verdana;">ON</span></sub></i><span style="font-family:Verdana;"> - </span><i><span style="font-family:Verdana;">I</span><sub><span style="font-family:Verdana;">OFF</span></sub></i><span style="font-family:Verdana;"> ratio,</span></span> <i><span style="font-family:Verdana;">DIBL</span></i></span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">,</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;"> etc. has been investigated and plotted through extensive TCAD simulations. The physical parameters considered in this </span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">paper</span></span></span><span><span><span style="font-family:""><span style="font-family:Verdana;"> are operating temperature </span><span><span style="font-family:Verdana;">(</span><i><span style="font-family:Verdana;">T</span><sub><span style="font-family:Verdana;">op</span></sub></i><span style="font-family:Verdana;">), channel doping concentration (</span><i><span style="font-family:Verdana;">N</span><sub><span style="font-family:Verdana;">c</span></sub></i><span style="font-family:Verdana;">), gate oxide thickness (</span><i><span style="font-family:Verdana;">t</span><sub><span style="font-family:Verdana;">ox</span></sub></i><span style="font-family:Verdana;">) an</span></span><span style="font-family:Verdana;">d Silicon film thickness (</span><i><span style="font-family:Verdana;">t</span><sub><span style="font-family:Verdana;">si</span></sub></i><span style="font-family:Verdana;">). It </span></span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">was</span></span></span><span><span><span style="font-family:""><span style="font-family:Verdana;"> observed that quantum confinement of </span><span style="font-family:Verdana;">charge </span><span style="font-family:Verdana;">carriers significantly affect</span></span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">ed</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;"> the performance characteristics (mostly the</span></span></span><span><span><span style="font-family:""><span style="font-family:Verdana;"> subth</span><span style="font-family:Verdana;">reshold characteristics) of the device and therefore, it cannot be ignored in</span><span style="font-family:Verdana;"> the </span><span style="font-family:Verdana;">subthreshold region</span></span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">-</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">based circuit design like in many previous research</span></span></span><span><span><span style="font-family:""><span style="font-family:Verdana;"> works. </span><span><span style="font-family:Verdana;">The ATLAS</span><sup><span style="font-family:Verdana;">TM</span></sup><span style="font-family:Verdana;"> device simulator has been used in this </span></span></span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">paper</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;"> to perform simu</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;">lation and parameter extraction. The TCAD analysis presented in the</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;"> manuscript can be incorporated for device modeling and device</span></span></span><span style="font-family:Verdana;"><span style="font-family:Verdana;"><span style="font-family:Verdana;"> matching. It can be used to illustrate exact device behavior and for proper device control.
基金supported by the Young Fund of the National Natural Science Foundation of China(No.11104226)the Ph D Start-Up Fund(No.11zx7132)
文摘This paper aims to simulate the I–V static characteristic of the enhancement-mode（E-mode） Npolar GaN metal–insulator–semiconductor field effect transistor（MISFET） with self-aligned source/drain regions.Firstly, with SILVACO TCAD device simulation, the drain–source current as a function of the gate–source voltage is calculated and the dependence of the drain–source current on the drain–source voltage in the case of different gate–source voltages for the device with a 0.62 m gate length is investigated. Secondly, a comparison is made with the experimental report. Lastly, the transfer characteristic with different gate lengths and different buffer layers has been performed. The results show that the simulation is in accord with the experiment at the gate length of 0.62 m and the short channel effect becomes pronounced as gate length decreases. The E-mode will not be held below a100 nm gate length unless both transversal scaling and vertical scaling are being carried out simultaneously.
基金supported by the Fund ofLiaoning Province Education Department(No.L2012028)
文摘We study the characteristics of short channel double-gate(DG) junctionless(JL) FETs by device simulation. OutputⅠ-Ⅴcharacteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed.Distributions of electron concentration,electric field and potential in the body channel region are also analyzed.Comparisons with conventional inversion-mode(IM) FETs,which can demonstrate the advantages of JL FETs,have also been performed.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60976068 and 60936005)Cultivation Fund of the Key Scientific and Technical Innovation Project, Ministry of Education of China (Grant No. 708083),Cultivation Fund of the Key Scientific and Technical Innovation Project, Ministry of Education of China (Grant No. 200807010010)
文摘Based on the exact resultant solution of two-dimensional Poisson＇s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor （CMOS）-based device in a nanoscale regime.
基金Project supported by the Council of Scientific&Industrial Research(CSIR),Government of India under the SRF Scheme(Sanction Letter No:08/237(0005)/2012-EMR-I)
文摘We propose a scaling theory for single gate Al In Sb/In Sb high electron mobility transistors（HEMTs） by solving the two-dimensional（2D） Poisson equation. In our model, the effective conductive path effect（ECPE） is taken into account to overcome the problems arising from the device scaling. The potential in the effective conducting path is developed and a simple scaling equation is derived. This equation is solved to obtain the minimum channel potential Φdeff,minand the new scaling factor α to model the subthreshold behavior of the HEMTs. The developed model minimizes the leakage current and improves the subthreshold swing degradation of the HEMTs. The results of the analytical model are verified by numerical simulation with a Sentaurus TCAD device simulator.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.12074046 and 12074115)the Hunan Provincial Natural Science Foundation of China(Grant Nos.2020JJ4597,2021JJ40558,and 2021JJ30733)+1 种基金the Scientific Research Fund of Hunan Provincial Education Department,China(Grant Nos.20K007 and 20C0039)the Key Projects of Changsha Science and Technology Plan(Grant No.kq1901102).
文摘We preform a first-principles study of performance of 5 nm double-gated(DG)Schottky-barrier field effect transistors(SBFETs)based on two-dimensional SiC with monolayer or bilayer metallic 1T-phase MoS_(2) contacts.Because of the wide bandgap of SiC,the corresponding DG SBFETs can weaken the short channel effect.The calculated transfer characteristics also meet the standard of the high performance transistor summarized by international technology road-map for semiconductors.Moreover,the bilayer metallic 1T-phase MoS_(2) contacts in three stacking structures all can further raise the ON-state currents of DG SiC SBFETs in varying degrees.The above results are helpful and instructive for design of short channel transistors in the future.
文摘Deep submicron partially depleted silicon on insulator （PDSOI） nMOSFETs were fabricated based on the 0.35μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences （IMECAS）. Mechanisms determining short-channel effects （SCE） in PDSOI nMOSFETs are clarified based on experimental results of threshold voltage dependence upon gate length. The effects of body bias, drain bias, temperature and body contact on the SCE have been investigated. The SCE in SOI devices is found to be dependent on body bias, drain bias and body contact. Floating body devices show a more severe reverse short channel effect （RSCE） than devices with body contact structure. Devices with low body bias and high drain bias show a more obvious SCE.
基金Project supported by the Ministry of Electronics and Information Technology(MEITy),Govt. of India under its Visvesvaraya PhD Scheme(PhD-MLA/4(55)/2015-16)
文摘The evolution of the traditional metal oxide semiconductor field effect transistor(MOSFET) from planar single gate devices into 3 D multiple gates has led to higher package density and high current drive.However, due to continuous scaling and as a consequent close proximity between source and drain in the nano-regime, these multigate devices have been found to suffer from performance degrading short channel effects(SCEs).In this paper, a three dimensional analytical model of a trigate MOSFET incorporating non-conventional structural techniques like silicon-on-insulator, gate and channel engineering in addition to gate oxide stack is presented.The electrostatic integrity and device capability of suppressing SCEs is investigated by deriving the potential distribution profile using the three dimensional Poisson’s equation along with suitable boundary conditions. The other device parameters like threshold voltage and subthreshold swing are produced from the surface potential model.The validity of the proposed structure is established by the close agreement among the results obtained from the analytical model and simulation results.
文摘Metal-oxide-semiconductor field-effect transistor(MOSFET)and complementary metal-oxide-semiconductor(CMOS)circuits are the foundation of integrated circuits development and the cornerstone of information infrastructure and artificial intelligence(AI)progress[1-3].However,as the physical scale of devices continues to shrink,Moore’s Law has faced limitations,and short channel effects(SCEs)have become increasingly severe[4,5].
基金supported by the National Natural Science Foundation of China(92464303,U23A20364,and 62274121)the Open Research Fund of Suzhou Laboratory(SZLAB-1508-2024-ZD014)+1 种基金the Fundamental Research Funds for the Central Universities(2042025kf0031)the Wuhan Industrial Innovation Joint Laboratory(2024050902040443)。
文摘Due to the increase in leakage current and the serious decrease of on/off ratio caused by short channel effect and medium tunneling effect,the continued scaling of silicon transistors has become an insurmountable obstacle for the semiconductor manufacturing industry moving forward.Two-dimensional(2D)semiconductor materials hold promise for achieving high speed and low-power switching characteristics under limit node size[1-10].
文摘This paper presents an in-depth analysis of junctionless double gate vertical slit FET（JLDG VeSFET）device under process variability.It has been observed that junctionless FETs（JLDG VeSFET） are significantly less sensitive to many process parameter variations due to their inherent device structure and geometric properties.Sensitivity analysis reveals that the slit width,oxide thickness,radius of the device,gate length and channel doping concentration imperceptibly affect the device performance of JLDG VeSFET in terms of variation in threshold voltage,on current,off current and subthreshold slope（Ssub） as compared to its junction based counterpart i.e.MOSFET,because various short channel effects are well controlled in this device.The maximum variation in off current for JLDG VeSFET due to variation in different devices parameters is 5.6% whereas this variation is 38.8% for the MOS junction based device.However,variation in doping concentration in the channel region displays a small deviation in the threshold voltage and on current characteristics of the MOSFET device as compared to JL DG VeSFET.
