The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of...The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.展开更多
车载通信是高速串行器与解串器(serializer and deserializer,SerDes)技术应用的一个重要领域。针对复杂车载环境中链路高频衰减导致的符号间干扰在高阶调制方式下更为严重的问题,引入深度学习方法,设计一种基于Transformer编码器结构...车载通信是高速串行器与解串器(serializer and deserializer,SerDes)技术应用的一个重要领域。针对复杂车载环境中链路高频衰减导致的符号间干扰在高阶调制方式下更为严重的问题,引入深度学习方法,设计一种基于Transformer编码器结构的低复杂度信道均衡方案,以提高接收信号质量。该方案将输入序列转换为抽象的表示向量,然后利用编码器层提取表示向量的特征信息,最后全连接层根据特征信息对信号进行分类,从而实现高速SerDes信道均衡。实验结果表明:与传统自适应算法和全连接神经网络模型相比,所提方案能够有效降低高频衰减导致的信号失真,在计算复杂度降低19%和24%的情况下接收信噪比增益分别为1.8 dB和0.9 dB。通过在高速SerDes系统中应用所提信道均衡方案,可以提高信号传输质量以及增强系统的鲁棒性。展开更多
文摘The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.
文摘车载通信是高速串行器与解串器(serializer and deserializer,SerDes)技术应用的一个重要领域。针对复杂车载环境中链路高频衰减导致的符号间干扰在高阶调制方式下更为严重的问题,引入深度学习方法,设计一种基于Transformer编码器结构的低复杂度信道均衡方案,以提高接收信号质量。该方案将输入序列转换为抽象的表示向量,然后利用编码器层提取表示向量的特征信息,最后全连接层根据特征信息对信号进行分类,从而实现高速SerDes信道均衡。实验结果表明:与传统自适应算法和全连接神经网络模型相比,所提方案能够有效降低高频衰减导致的信号失真,在计算复杂度降低19%和24%的情况下接收信噪比增益分别为1.8 dB和0.9 dB。通过在高速SerDes系统中应用所提信道均衡方案,可以提高信号传输质量以及增强系统的鲁棒性。
