The on-chip memory performance of embedded systems directly affects the system designers＇ decision about how to allocate expensive silicon area. A novel memory architecture, flexible sequential and random access memo...The on-chip memory performance of embedded systems directly affects the system designers＇ decision about how to allocate expensive silicon area. A novel memory architecture, flexible sequential and random access memory （FSRAM）, is investigated for embedded systems. To realize sequential accesses, small “links”are added to each row in the RAM array to point to the next row to be prefetched. The potential cache pollution is ameliorated by a small sequential access buyer （SAB）. To evaluate the architecture-level performance of FSRAM, we ran the Mediabench benchmark programs on a modified version of the SimpleScalar simulator. Our results show that the FSRAM improves the performance of a baseline processor with a 16KB data cache up to 55%, with an average of 9%; furthermore, the FSRAM reduces 53.1% of the data cache miss count on average due to its prefetching effect. We also designed RTL and SPICE models of the FSRAM, which show that the FSRAM significantly improves memory access time, while reducing power consumption, with negligible area overhead.展开更多
The soil-rock mixture(SRM) is highly heterogeneous. Before carrying out numerical analysis,a structure model should be generated. A reliable way to obtain such structure is by generating random aggregate structure bas...The soil-rock mixture(SRM) is highly heterogeneous. Before carrying out numerical analysis,a structure model should be generated. A reliable way to obtain such structure is by generating random aggregate structure based on random sequential addition(RSA). The classical RSA is neither efficient nor robust since valid positions to place new inclusions are formulated by trial, which involves repetitive overlapping tests. In this paper, the algorithm of Entrance block between block A and B(EAB)is synergized with background mesh to redesign RSA so that permissible positions to place new inclusions can be predicted,resulting in dramatic improvement in efficiency and robustness.展开更多
文摘The on-chip memory performance of embedded systems directly affects the system designers＇ decision about how to allocate expensive silicon area. A novel memory architecture, flexible sequential and random access memory （FSRAM）, is investigated for embedded systems. To realize sequential accesses, small “links”are added to each row in the RAM array to point to the next row to be prefetched. The potential cache pollution is ameliorated by a small sequential access buyer （SAB）. To evaluate the architecture-level performance of FSRAM, we ran the Mediabench benchmark programs on a modified version of the SimpleScalar simulator. Our results show that the FSRAM improves the performance of a baseline processor with a 16KB data cache up to 55%, with an average of 9%; furthermore, the FSRAM reduces 53.1% of the data cache miss count on average due to its prefetching effect. We also designed RTL and SPICE models of the FSRAM, which show that the FSRAM significantly improves memory access time, while reducing power consumption, with negligible area overhead.
基金supported by the National Basic Research Program of China(973 Program)(Grant No.2014CB047100)the National Natural Science Foundation of China(Grant Nos.11572009,51538001 and 51609240)
文摘The soil-rock mixture(SRM) is highly heterogeneous. Before carrying out numerical analysis,a structure model should be generated. A reliable way to obtain such structure is by generating random aggregate structure based on random sequential addition(RSA). The classical RSA is neither efficient nor robust since valid positions to place new inclusions are formulated by trial, which involves repetitive overlapping tests. In this paper, the algorithm of Entrance block between block A and B(EAB)is synergized with background mesh to redesign RSA so that permissible positions to place new inclusions can be predicted,resulting in dramatic improvement in efficiency and robustness.
