An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an intern...An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.展开更多
Static random-access memory(SRAM)-based eld programmable gate arrays(FPGAs)are sensitive to radiationinduced single event upsets(SEUs)^([1]).Single-bit upsets(SBUs),as a well-known effect in FPGAs,occur when the energ...Static random-access memory(SRAM)-based eld programmable gate arrays(FPGAs)are sensitive to radiationinduced single event upsets(SEUs)^([1]).Single-bit upsets(SBUs),as a well-known effect in FPGAs,occur when the energy deposited by a single particle(such as heavy ion)exceeds the critical charge in single memory cell.However,in modern advanced process technologies,owing to the smaller area and decreased critical charge of transistors.展开更多
According to the SRAM-based FPGA's single event effect problem in space application,single event upset induced multi-block error(SEU-MBE) phenomenon and its mitigation strategy are studied in the paper.After analy...According to the SRAM-based FPGA's single event effect problem in space application,single event upset induced multi-block error(SEU-MBE) phenomenon and its mitigation strategy are studied in the paper.After analyzing the place and route result,the paper points out that the essence of SEU-MBE is that some important modules exceed the safe internal distance.Two approaches,area constraint method(ACM) and incremental route algorithm(IRA),are proposed,which can reduce the error rate by manipulating programmable switch matrix and interconnection points within FPGA route resource.Fault injection experiments indicate that error detection rate is above 98.6% for both strategies,and FPGA resources increment and performance penalty are around 10%.展开更多
As the ASIC design cost becomes affordable only for very large-scale productions, the FPGA technology is currently becoming the leading technology for those applications that require a small-scale production. FPGAs ca...As the ASIC design cost becomes affordable only for very large-scale productions, the FPGA technology is currently becoming the leading technology for those applications that require a small-scale production. FPGAs can be considered as a technology crossing between hardware and software. Only a small-number of standards for the design of safety-critical systems give guidelines and recommendations that take the peculiarities of the FPGA technology into consideration. The main contribution of this paper is an overview of the existing design standards that regulate the design and verification of FPCA-based systems in safety-critical application fields. Moreover, the paper proposes a survey of significant published research proposals and existing industrial guidelines about the topic, and collects and reports about some lessons learned from industrial and research projects involving the use of FPGA devices.展开更多
SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets （SEUs） in space applications. The failure mechanism in FPGA＇s configuration memory differs from those in traditional memory device. As ...SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets （SEUs） in space applications. The failure mechanism in FPGA＇s configuration memory differs from those in traditional memory device. As a result, there is a growing demand for methodologies which could quantitatively evaluate the impact of this effect. Fault injection appears to meet such requirement. In this paper, we propose a new methodology to analyze the soft errors in SRAM-based FPGAs. This method is based on in depth understanding of the device architecture and failure mechanisms induced by configuration upsets. The developed programs read in the placed and routed netlist, search for critical logic nodes and paths that may destroy the circuit topological structure, and then query a database storing the decoded relationship of the configurable resources and corresponding control bit to get the sensitive bits. Accelerator irradiation test and fault injection experiments were carried out to validate this approach.展开更多
We present an input/output block （lOB） array used in the radiation-hardened SRAM-based field- programmable gate array （FPGA） VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-in...We present an input/output block （lOB） array used in the radiation-hardened SRAM-based field- programmable gate array （FPGA） VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator （SOI） logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the pro- grammable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different ca- pacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS 1000 chip with an IOB array has a total dose tolerance of 100 krad（Si）, a dose survivability rate of 1.5 × 10^11 rad（Si）/s, and a neutron fluence immunity of 1×10^14 n/cm2.展开更多
基金Supported by the National High Technology and Development Program of China(2013AA1548)
文摘An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.
基金National Natural Science Foundation of China(12035019,11690041)。
文摘Static random-access memory(SRAM)-based eld programmable gate arrays(FPGAs)are sensitive to radiationinduced single event upsets(SEUs)^([1]).Single-bit upsets(SBUs),as a well-known effect in FPGAs,occur when the energy deposited by a single particle(such as heavy ion)exceeds the critical charge in single memory cell.However,in modern advanced process technologies,owing to the smaller area and decreased critical charge of transistors.
基金supported by the National High Technology Research and Development Program of China ("863" Program) (Grant No. 2006SQ710375)the Civil Aerospace Technologies Advanced Research Pro-gram of China (Grant No. C1320061301)Ministries and Commissions’Advanced Research Found of China (Grant No. 9140A20070209KG0160)
文摘According to the SRAM-based FPGA's single event effect problem in space application,single event upset induced multi-block error(SEU-MBE) phenomenon and its mitigation strategy are studied in the paper.After analyzing the place and route result,the paper points out that the essence of SEU-MBE is that some important modules exceed the safe internal distance.Two approaches,area constraint method(ACM) and incremental route algorithm(IRA),are proposed,which can reduce the error rate by manipulating programmable switch matrix and interconnection points within FPGA route resource.Fault injection experiments indicate that error detection rate is above 98.6% for both strategies,and FPGA resources increment and performance penalty are around 10%.
文摘As the ASIC design cost becomes affordable only for very large-scale productions, the FPGA technology is currently becoming the leading technology for those applications that require a small-scale production. FPGAs can be considered as a technology crossing between hardware and software. Only a small-number of standards for the design of safety-critical systems give guidelines and recommendations that take the peculiarities of the FPGA technology into consideration. The main contribution of this paper is an overview of the existing design standards that regulate the design and verification of FPCA-based systems in safety-critical application fields. Moreover, the paper proposes a survey of significant published research proposals and existing industrial guidelines about the topic, and collects and reports about some lessons learned from industrial and research projects involving the use of FPGA devices.
基金Project supported by the National Natural Science Foundation of China(No.10875096).
文摘SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets （SEUs） in space applications. The failure mechanism in FPGA＇s configuration memory differs from those in traditional memory device. As a result, there is a growing demand for methodologies which could quantitatively evaluate the impact of this effect. Fault injection appears to meet such requirement. In this paper, we propose a new methodology to analyze the soft errors in SRAM-based FPGAs. This method is based on in depth understanding of the device architecture and failure mechanisms induced by configuration upsets. The developed programs read in the placed and routed netlist, search for critical logic nodes and paths that may destroy the circuit topological structure, and then query a database storing the decoded relationship of the configurable resources and corresponding control bit to get the sensitive bits. Accelerator irradiation test and fault injection experiments were carried out to validate this approach.
文摘We present an input/output block （lOB） array used in the radiation-hardened SRAM-based field- programmable gate array （FPGA） VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator （SOI） logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the pro- grammable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different ca- pacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS 1000 chip with an IOB array has a total dose tolerance of 100 krad（Si）, a dose survivability rate of 1.5 × 10^11 rad（Si）/s, and a neutron fluence immunity of 1×10^14 n/cm2.
