An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an intern...An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.展开更多
Static random-access memory(SRAM)-based eld programmable gate arrays(FPGAs)are sensitive to radiationinduced single event upsets(SEUs)^([1]).Single-bit upsets(SBUs),as a well-known effect in FPGAs,occur when the energ...Static random-access memory(SRAM)-based eld programmable gate arrays(FPGAs)are sensitive to radiationinduced single event upsets(SEUs)^([1]).Single-bit upsets(SBUs),as a well-known effect in FPGAs,occur when the energy deposited by a single particle(such as heavy ion)exceeds the critical charge in single memory cell.However,in modern advanced process technologies,owing to the smaller area and decreased critical charge of transistors.展开更多
基于系统级封装(System in a Package, SiP)技术的SRAM型FPGA微系统广泛应用于航天领域。由于微系统复杂的封装结构,限制了大多数传统失效分析设备与分析方式的应用。针对微系统器件的故障诊断困难、测试流程复杂等可靠性问题,开展了常...基于系统级封装(System in a Package, SiP)技术的SRAM型FPGA微系统广泛应用于航天领域。由于微系统复杂的封装结构,限制了大多数传统失效分析设备与分析方式的应用。针对微系统器件的故障诊断困难、测试流程复杂等可靠性问题,开展了常见故障分析研究。对SRAM配置固有缺陷和FPGA内部配置刷新电路异常等典型故障的产生机理进行了深入分析和总结。结合理论分析和问题现象,提出了配置位回读校验测试及比对、辅助电源VCC, AUX电流参数一致性控制等测试筛选方法,有效提升了测试覆盖性。利用相应测试手段和数据分析方法,可精准定位失效机理与失效部位,对后续宇航用SRAM型FPGA微系统应用及筛选有重要意义。展开更多
The high-speed computational performance is gained at the cost of huge hardware resource,which restricts the application of high-accuracy algorithms because of the limited hardware cost in practical use.To solve the p...The high-speed computational performance is gained at the cost of huge hardware resource,which restricts the application of high-accuracy algorithms because of the limited hardware cost in practical use.To solve the problem,a novel method for designing the field programmable gate array(FPGA)-based non-uniform rational B-spline(NURBS) interpolator and motion controller,which adopts the embedded multiprocessor technique,is proposed in this study.The hardware and software design for the multiprocessor,one of which is for NURBS interpolation and the other for position servo control,is presented.Performance analysis and experiments on an X-Y table are carried out,hardware cost as well as consuming time for interpolation and motion control is compared with the existing methods.The experimental and comparing results indicate that,compared with the existing methods,the proposed method can reduce the hardware cost by 97.5% using higher-accuracy interpolation algorithm within the period of 0.5 ms.A method which ensures the real-time performance and interpolation accuracy,and reduces the hardware cost significantly is proposed,and it’s practical in the use of industrial application.展开更多
In order to capture and storage video data real-time for carrier-based photoelectric warning system, An acquisition and storage system based on FPGA is designed. To complete the asynchronous interface timing of the ca...In order to capture and storage video data real-time for carrier-based photoelectric warning system, An acquisition and storage system based on FPGA is designed. To complete the asynchronous interface timing of the camera and the storage system, the video data which come from infrared camera and visible light camera is stored to FIFO by FPGA, and then four SDRAM as cache and ping-pong operation cache-data storage to the CF card, this structure not only takes advantage of high-speed reading and writing skills of CF card, but also to ensure the integrity of the video data. In the final experiment proved that the system can be effectively applied to ships the photoelectric warning scanning system, its performance fully meet the needs of practical application.展开更多
In order to ensure stable,correct and real-time high-speed transmission of indoor visible light communication(VLC),the key modulation and demodulation technologies of orthogonal frequency division multiplexing(OFDM) a...In order to ensure stable,correct and real-time high-speed transmission of indoor visible light communication(VLC),the key modulation and demodulation technologies of orthogonal frequency division multiplexing(OFDM) are studied in this paper. The time-domain synchronization,frequency synchronization and channel equalization of receiver are analyzed and optimized by utilizing short and long training preamble. Moreover,field programmable gate array(FPGA) development board(Xilinx Kintex-7) and Verilog hardware description language are used to realize the design of proposed OFDM-VLC system. Simulation and experiment both verify the feasibility of the hardware designs of this system. The proposed OFDM-based VLC system can process signal in real-time,which can be used in actual VLC application systems.展开更多
介绍一种新型静态存储器———QDR(Quad Data Rate)SRAM的存储器结构、与系统的接口连接、主要的操作时序。参考实际QDR存储器内部组成,利用FPGA实现存储器控制器的设计实现。旨在通过FPGA的快速、灵活、容易修改的特点,设计并实现在高...介绍一种新型静态存储器———QDR(Quad Data Rate)SRAM的存储器结构、与系统的接口连接、主要的操作时序。参考实际QDR存储器内部组成,利用FPGA实现存储器控制器的设计实现。旨在通过FPGA的快速、灵活、容易修改的特点,设计并实现在高速数据通信系统中,QDR静态存储器用于处理器和接口连接的外设之间的数据交换。着重分析QDR控制器的读/写操作状态机。展开更多
基金Supported by the National High Technology and Development Program of China(2013AA1548)
文摘An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.
基金National Natural Science Foundation of China(12035019,11690041)。
文摘Static random-access memory(SRAM)-based eld programmable gate arrays(FPGAs)are sensitive to radiationinduced single event upsets(SEUs)^([1]).Single-bit upsets(SBUs),as a well-known effect in FPGAs,occur when the energy deposited by a single particle(such as heavy ion)exceeds the critical charge in single memory cell.However,in modern advanced process technologies,owing to the smaller area and decreased critical charge of transistors.
文摘基于系统级封装(System in a Package, SiP)技术的SRAM型FPGA微系统广泛应用于航天领域。由于微系统复杂的封装结构,限制了大多数传统失效分析设备与分析方式的应用。针对微系统器件的故障诊断困难、测试流程复杂等可靠性问题,开展了常见故障分析研究。对SRAM配置固有缺陷和FPGA内部配置刷新电路异常等典型故障的产生机理进行了深入分析和总结。结合理论分析和问题现象,提出了配置位回读校验测试及比对、辅助电源VCC, AUX电流参数一致性控制等测试筛选方法,有效提升了测试覆盖性。利用相应测试手段和数据分析方法,可精准定位失效机理与失效部位,对后续宇航用SRAM型FPGA微系统应用及筛选有重要意义。
基金supported by National Key Basic Research Program of China(973 ProgramGrant No.2011CB706804)+1 种基金Shanghai Municipal Science and Technology Commission of China(Grant No.11QH1401400)Research Project of State Key Laboratory of Mechanical System & Vibration of China(Grant No.MSVMS201102)
文摘The high-speed computational performance is gained at the cost of huge hardware resource,which restricts the application of high-accuracy algorithms because of the limited hardware cost in practical use.To solve the problem,a novel method for designing the field programmable gate array(FPGA)-based non-uniform rational B-spline(NURBS) interpolator and motion controller,which adopts the embedded multiprocessor technique,is proposed in this study.The hardware and software design for the multiprocessor,one of which is for NURBS interpolation and the other for position servo control,is presented.Performance analysis and experiments on an X-Y table are carried out,hardware cost as well as consuming time for interpolation and motion control is compared with the existing methods.The experimental and comparing results indicate that,compared with the existing methods,the proposed method can reduce the hardware cost by 97.5% using higher-accuracy interpolation algorithm within the period of 0.5 ms.A method which ensures the real-time performance and interpolation accuracy,and reduces the hardware cost significantly is proposed,and it’s practical in the use of industrial application.
文摘In order to capture and storage video data real-time for carrier-based photoelectric warning system, An acquisition and storage system based on FPGA is designed. To complete the asynchronous interface timing of the camera and the storage system, the video data which come from infrared camera and visible light camera is stored to FIFO by FPGA, and then four SDRAM as cache and ping-pong operation cache-data storage to the CF card, this structure not only takes advantage of high-speed reading and writing skills of CF card, but also to ensure the integrity of the video data. In the final experiment proved that the system can be effectively applied to ships the photoelectric warning scanning system, its performance fully meet the needs of practical application.
基金supported by the National High Technology Research and Development Program of China(863 Program)(No.2015AA033303)the National Key Basic Research Program of China(973 program)(No.2013CB329204)+1 种基金the National Nature Science Foundation of China(Nos.61178051,61321063 and 61335010)the Science and Technology Project of Guangdong Province in China(No.2014B010120004)
文摘In order to ensure stable,correct and real-time high-speed transmission of indoor visible light communication(VLC),the key modulation and demodulation technologies of orthogonal frequency division multiplexing(OFDM) are studied in this paper. The time-domain synchronization,frequency synchronization and channel equalization of receiver are analyzed and optimized by utilizing short and long training preamble. Moreover,field programmable gate array(FPGA) development board(Xilinx Kintex-7) and Verilog hardware description language are used to realize the design of proposed OFDM-VLC system. Simulation and experiment both verify the feasibility of the hardware designs of this system. The proposed OFDM-based VLC system can process signal in real-time,which can be used in actual VLC application systems.
文摘介绍一种新型静态存储器———QDR(Quad Data Rate)SRAM的存储器结构、与系统的接口连接、主要的操作时序。参考实际QDR存储器内部组成,利用FPGA实现存储器控制器的设计实现。旨在通过FPGA的快速、灵活、容易修改的特点,设计并实现在高速数据通信系统中,QDR静态存储器用于处理器和接口连接的外设之间的数据交换。着重分析QDR控制器的读/写操作状态机。
