A modified four transistor （4T） self-body-bias structured SRAM/SOI memory cell is proposed. The structure is designed and its parameters are obtained by performance simulation and analysis with TSUPREM4 and MEDICI.T...A modified four transistor （4T） self-body-bias structured SRAM/SOI memory cell is proposed. The structure is designed and its parameters are obtained by performance simulation and analysis with TSUPREM4 and MEDICI.The structure saves area and its process is simplified by using the body resistor with buried p^＋ channel beneath the nMOS gate instead of the pMOS of 6T CMOS SRAM. Furthermore, this structure can operate safely with a 0.5V supply voltage, which may be prevalent in the near future. Finally, compared to conventional 6T CMOS SRAM,this structure＇s transient responses are normal and its power dissipation is 10 times smaller.展开更多
为提升SRAM型FPGA电路块存储器和配置存储器抗单粒子翻转性能,本文提出一种脉冲屏蔽SRAM单元结构。该结构通过在标准的六管单元中加入延迟结构,增大单元对单粒子事件响应时间,实现对粒子入射产生的脉冲电流屏蔽作用。以64k SRAM作为验...为提升SRAM型FPGA电路块存储器和配置存储器抗单粒子翻转性能,本文提出一种脉冲屏蔽SRAM单元结构。该结构通过在标准的六管单元中加入延迟结构,增大单元对单粒子事件响应时间,实现对粒子入射产生的脉冲电流屏蔽作用。以64k SRAM作为验证电路进行单粒子翻转性能对比,电路的抗单粒子翻转阈值由采用标准六管单元的抗单粒子翻转阈值大于25 Me V·cm2·mg-1提升至大于45 Me V·cm2·mg-1,加固单元面积较标准六管单元增大约21.3%。30万门级抗辐照FPGA电路通过脉冲屏蔽单元结合抗辐照SOI工艺实现,其抗辐照指标分别为:抗单粒子翻转阈值大于37.3 Me V·cm2·mg-1,抗单粒子锁定阈值大于99.8 Me V·cm2·mg-1,抗电离总剂量能力大于200 krad(Si)。展开更多
针对宇航用大容量SRAM器件抗单粒子效应性能的试验评估需要,利用重离子加速器对抗辐射加固32 M Bulk CMOS工艺SRAM和16 M SOI CMOS工艺SRAM进行了单粒子效应模拟试验研究,获得SRAM器件单粒子效应特性并进行在轨翻转率预估;对单粒子翻转...针对宇航用大容量SRAM器件抗单粒子效应性能的试验评估需要,利用重离子加速器对抗辐射加固32 M Bulk CMOS工艺SRAM和16 M SOI CMOS工艺SRAM进行了单粒子效应模拟试验研究,获得SRAM器件单粒子效应特性并进行在轨翻转率预估;对单粒子翻转试验中重离子射程的影响,不同SEU类型的翻转截面差异,在轨翻转率预估的有关因素等进行了分析讨论。结果表明,这2款抗辐射加固SRAM器件都达到了较高的抗单粒子效应性能指标。试验结果可以为SRAM器件的单粒子效应试验评估提供参考。展开更多
In this work single event upset(SEU) sensitivity of 45 nm fully depleted silicon-on-insulator(FDSOI) static random access memory(SRAM) cell and that of SOI fin-shaped field-effect-transistor(FinFET) SRAM cell have bee...In this work single event upset(SEU) sensitivity of 45 nm fully depleted silicon-on-insulator(FDSOI) static random access memory(SRAM) cell and that of SOI fin-shaped field-effect-transistor(FinFET) SRAM cell have been investigated by 3D TCAD simulations.The critical charges and SEU threshold linear energy transfer(LET) value of the two SRAM cells are consistent due to similar gate capacitance.The low electrical field and the high recombination rate account for the non-sensitivity to SEU in heavily doped drain region.Compared with FDSOI SRAM,SOI FinFET SRAM cell exhibits lower SEU sensitivity at the center of the gate.The smaller sensitive area in SOI FinFET SRAM cell may result in a smaller SEU saturation cross section than that of SOI FinFET SRAM.展开更多
A novel SEU hardened 10T PD SOI SRAM cell is proposed. By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors, this cell suppresses the parasitic BJT and source-...A novel SEU hardened 10T PD SOI SRAM cell is proposed. By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors, this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOI transistor which causes the SEU in PD SOI SRAM. Mixed-mode simulation shows that this novel cell completely solves the SEU, where the ion affects the single transistor. Through analysis of the upset mechanism of this novel cell, SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references. To achieve this, the new cell adds four transistors and has a 43.4% area overhead and performance penalty.展开更多
文摘A modified four transistor （4T） self-body-bias structured SRAM/SOI memory cell is proposed. The structure is designed and its parameters are obtained by performance simulation and analysis with TSUPREM4 and MEDICI.The structure saves area and its process is simplified by using the body resistor with buried p^＋ channel beneath the nMOS gate instead of the pMOS of 6T CMOS SRAM. Furthermore, this structure can operate safely with a 0.5V supply voltage, which may be prevalent in the near future. Finally, compared to conventional 6T CMOS SRAM,this structure＇s transient responses are normal and its power dissipation is 10 times smaller.
文摘为提升SRAM型FPGA电路块存储器和配置存储器抗单粒子翻转性能,本文提出一种脉冲屏蔽SRAM单元结构。该结构通过在标准的六管单元中加入延迟结构,增大单元对单粒子事件响应时间,实现对粒子入射产生的脉冲电流屏蔽作用。以64k SRAM作为验证电路进行单粒子翻转性能对比,电路的抗单粒子翻转阈值由采用标准六管单元的抗单粒子翻转阈值大于25 Me V·cm2·mg-1提升至大于45 Me V·cm2·mg-1,加固单元面积较标准六管单元增大约21.3%。30万门级抗辐照FPGA电路通过脉冲屏蔽单元结合抗辐照SOI工艺实现,其抗辐照指标分别为:抗单粒子翻转阈值大于37.3 Me V·cm2·mg-1,抗单粒子锁定阈值大于99.8 Me V·cm2·mg-1,抗电离总剂量能力大于200 krad(Si)。
文摘针对宇航用大容量SRAM器件抗单粒子效应性能的试验评估需要,利用重离子加速器对抗辐射加固32 M Bulk CMOS工艺SRAM和16 M SOI CMOS工艺SRAM进行了单粒子效应模拟试验研究,获得SRAM器件单粒子效应特性并进行在轨翻转率预估;对单粒子翻转试验中重离子射程的影响,不同SEU类型的翻转截面差异,在轨翻转率预估的有关因素等进行了分析讨论。结果表明,这2款抗辐射加固SRAM器件都达到了较高的抗单粒子效应性能指标。试验结果可以为SRAM器件的单粒子效应试验评估提供参考。
基金supported by the National Natural Science Foundation of China (Grant No. 11175138)the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 20100201110018)the Key Program of the National Natural Science Foundation of China (Grant No. 11235008)
文摘In this work single event upset(SEU) sensitivity of 45 nm fully depleted silicon-on-insulator(FDSOI) static random access memory(SRAM) cell and that of SOI fin-shaped field-effect-transistor(FinFET) SRAM cell have been investigated by 3D TCAD simulations.The critical charges and SEU threshold linear energy transfer(LET) value of the two SRAM cells are consistent due to similar gate capacitance.The low electrical field and the high recombination rate account for the non-sensitivity to SEU in heavily doped drain region.Compared with FDSOI SRAM,SOI FinFET SRAM cell exhibits lower SEU sensitivity at the center of the gate.The smaller sensitive area in SOI FinFET SRAM cell may result in a smaller SEU saturation cross section than that of SOI FinFET SRAM.
文摘A novel SEU hardened 10T PD SOI SRAM cell is proposed. By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors, this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOI transistor which causes the SEU in PD SOI SRAM. Mixed-mode simulation shows that this novel cell completely solves the SEU, where the ion affects the single transistor. Through analysis of the upset mechanism of this novel cell, SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references. To achieve this, the new cell adds four transistors and has a 43.4% area overhead and performance penalty.
