This paper explores the impact of back-gate bias (V_(soi)) and supply voltage (V_(DD)) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) unde...This paper explores the impact of back-gate bias (V_(soi)) and supply voltage (V_(DD)) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) under high linear energy transfer heavyion experimentation.The experimental findings demonstrate that applying a negative back-gate bias to NMOS and a positive back-gate bias to PMOS enhances the SEU resistance of SRAM.Specifically,as the back-gate bias for N-type transistors(V_(nsoi)) decreases from 0 to-10 V,the SEU cross section decreases by 93.23%,whereas an increase in the back-gate bias for P-type transistors (V_(psoi)) from 0 to 10 V correlates with an 83.7%reduction in SEU cross section.Furthermore,a significant increase in the SEU cross section was observed with increase in supply voltage,as evidenced by a 159%surge at V_(DD)=1.98 V compared with the nominal voltage of 1.8 V.To explore the physical mechanisms underlying these experimental data,we analyzed the dependence of the critical charge of the circuit and the collected charge on the bias voltage by simulating SEUs using technology computer-aided design.展开更多
In recent years,carbon nanotube field effect transistor(CNTFET)has become an attractive alternative to silicon for designing high-performance,highly stable,and low-power static random access memory(SRAM).SRAM serves a...In recent years,carbon nanotube field effect transistor(CNTFET)has become an attractive alternative to silicon for designing high-performance,highly stable,and low-power static random access memory(SRAM).SRAM serves as a cache memory in computers and many portable devices.Carbon nanotubes(CNTs),because of their exceptional transport capabilities,outstanding thermal conductivities,and impressive current handling capacities,have demonstrated great potential as an alternative device to the standard complementary metal-oxide-semiconductor(CMOS).The SRAM cell design using CNTFET is being compared to SRAM cell designs built using traditional CMOS technology.This paper presents the comprehensive analysis of CMOS&CNTFET based 8T SRAM cell design.Because of the nanoscale size,ballistic transport,and higher carrier mobility of the semiconducting nanotubes in CNTFET,it is integrated into the 8T SRAM cell.The approach incorporates several nonidealities,including the presence of quantum confinement consequences in the peripheral and transverse prescriptions,acoustic and transparent photon diffraction in the region surrounding the channel,as well as the screening effects by parallel CNTs in CNTFETs with multiple CNTs.By incorporating Stanford University CNTFET model in CADENCE(virtuoso)32 nm simulation,we have found that CNTFET SRAM cell is 4 times faster in terms of write/read delay and the write/read power delay product(PDP)value is almost 5 times lower compared to CMOS based SRAM.We have also analyzed the effect of temperature&different tube positions of CNTs on the performance evaluation of the 8T SRAM cell.展开更多
Artificial intelligence(AI)processes data-centric applications with minimal effort.However,it poses new challenges to system design in terms of computational speed and energy efficiency.The traditional von Neumann arc...Artificial intelligence(AI)processes data-centric applications with minimal effort.However,it poses new challenges to system design in terms of computational speed and energy efficiency.The traditional von Neumann architecture cannot meet the requirements of heavily datacentric applications due to the separation of computation and storage.The emergence of computing inmemory(CIM)is significant in circumventing the von Neumann bottleneck.A commercialized memory architecture,static random-access memory(SRAM),is fast and robust,consumes less power,and is compatible with state-of-the-art technology.This study investigates the research progress of SRAM-based CIM technology in three levels:circuit,function,and application.It also outlines the problems,challenges,and prospects of SRAM-based CIM macros.展开更多
A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event ups...A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm^(2)).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm^(2)),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm^(2))owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm^(2))),the benefit of the EDAC code is reduced significantly because the multi-bit upset proportion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distributions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some suggestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.展开更多
An approach to design small scale CMOS static random access memory (SRAM) is proposed. The design of address decoder, memory cell, and the layout are included. This approach adopts flip-flop array structure. The flip-...An approach to design small scale CMOS static random access memory (SRAM) is proposed. The design of address decoder, memory cell, and the layout are included. This approach adopts flip-flop array structure. The flip-flops are used as the storage cells and they are stacked to form the whole SRAM module. The word select bit is generated from the address decoder. And one word at a time is selected for reading or writing. The design of the memory core's layout is also discussed since it should be optimized to save area and also should be convenient for realization. It's a full-custom layout. The address decoder is composed of combinational logic circuit and its layout is also designed as a full-custom layout. With all these modules, the integral structure of the SRAM is carried out.展开更多
A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power ga...A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM). The experiment results show that PBTI has significant influence on the read and write operations of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 106 s working time. Then, a circuit level simulation was used to verify the assumption of the SPAP model, and finally the statistic data of CPU2000 benchmarks show that the proposed model has a reduction of 3.85% for estimation of the SNM degradation after 106 s working time compared with previous work.展开更多
An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an intern...An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.展开更多
The 28 nm process has a high cost-performance ratio and has gradually become the standard for the field of radiation-hardened devices.However,owing to the minimum physical gate length of only 35 nm,the physical area o...The 28 nm process has a high cost-performance ratio and has gradually become the standard for the field of radiation-hardened devices.However,owing to the minimum physical gate length of only 35 nm,the physical area of a standard 6T SRAM unit is approximately 0.16μm^(2),resulting in a significant enhancement of multi-cell charge-sharing effects.Multiple-cell upsets(MCUs)have become the primary physical mechanism behind single-event upsets(SEUs)in advanced nanometer node devices.The range of ionization track effects increases with higher ion energies,and spacecraft in orbit primarily experience SEUs caused by high-energy ions.However,ground accelerator experiments have mainly obtained low-energy ion irradiation data.Therefore,the impact of ion energy on the SEU cross section,charge collection mechanisms,and MCU patterns and quantities in advanced nanometer devices remains unclear.In this study,based on the experimental platform of the Heavy Ion Research Facility in Lanzhou,low-and high-energy heavy-ion beams were used to study the SEUs of 28 nm SRAM devices.The influence of ion energy on the charge collection processes of small-sensitive-volume devices,MCU patterns,and upset cross sections was obtained,and the applicable range of the inverse cosine law was clarified.The findings of this study are an important guide for the accurate evaluation of SEUs in advanced nanometer devices and for the development of radiation-hardening techniques.展开更多
The pattern dependence in synergistic effects was studied in a 0.18 μm static random access memory（SRAM） circuit.Experiments were performed under two SEU test environments：3 Me V protons and heavy ions.Measured re...The pattern dependence in synergistic effects was studied in a 0.18 μm static random access memory（SRAM） circuit.Experiments were performed under two SEU test environments：3 Me V protons and heavy ions.Measured results show different trends.In heavy ion SEU test,the degradation in the peripheral circuitry also existed because the measured SEU cross section decreased regardless of the patterns written to the SRAM array.TCAD simulation was performed.TIDinduced degradation in n MOSFETs mainly induced the imprint effect in the SRAM cell,which is consistent with the measured results under the proton environment,but cannot explain the phenomena observed under heavy ion environment.A possible explanation could be the contribution from the radiation-induced GIDL in pMOSFETs.展开更多
Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the ...Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the evolution of M3D integration from traditional bulk semiconductors to low-dimensional materials like two-dimensioanl(2D)transition metal dichalcogenides(TMDCs)and carbon nanotubes(CNTs).Key applications include logic circuits,static random access memory(SRAM),resistive random access memory(RRAM),sensors,optoelectronics,and artificial intelligence(AI)processing.M3D integration enhances device performance by reducing footprint,improving power efficiency,and alleviating the von Neumann bottleneck.The integration of 2D materials in M3D structures demonstrates significant advancements in terms of scalability,energy efficiency,and functional diversity.Challenges in manufacturing and scaling are discussed,along with prospects for future research directions.Overall,the M3D integration with low-dimensional materials presents a promising pathway for the development of next-generation electronic devices and systems.展开更多
In this paper, the characterization of single event multiple cell upsets(MCUs) in a custom SRAM is performed in a 65 nm triple-well CMOS technology, and O(linear energy transfer(LET) = 3.1 Me V cm2/mg), Ti(LET = 22.2 ...In this paper, the characterization of single event multiple cell upsets(MCUs) in a custom SRAM is performed in a 65 nm triple-well CMOS technology, and O(linear energy transfer(LET) = 3.1 Me V cm2/mg), Ti(LET = 22.2 Me V cm2/mg) and Ge(LET = 37.4 Me V cm2/mg) particles are employed. The experimental results show that the percentage of MCU events in total upset events is 71.11%, 83.47% and 85.53% at O, Ti and Ge exposures. Moreover, due to the vertical well isolation layout, 100%(O), 100%(Ti) and 98.11%(Ge) MCU cluster just present at one or two adjacent columns, but there are still 4 cell upsets in one MCU cluster appearing on the same word wire. The characterization indicates that MCUs have become the main source of soft errors in SRAM, and even though combining the storage array interleaving distance(ID) scheme with the error detection and correction(EDAC) technique, the MCUs cannot be completely eliminated, new radiation hardened by design techniques still need to be further studied.展开更多
A power balance static random-access memory（SRAM） for resistance to differential power analysis（DPA） is proposed. In the proposed design, the switch power consumption and short-circuit power consumption are balanc...A power balance static random-access memory（SRAM） for resistance to differential power analysis（DPA） is proposed. In the proposed design, the switch power consumption and short-circuit power consumption are balanced by discharging and pre-charging the key nodes of the output circuit and adding an additional shortcircuit current path. Thus, the power consumption is constant in every read cycle. As a result, the DPA-resistant ability of the SRAM is improved. In 65 nm CMOS technology, the power balance SRAM is fully custom designed with a layout area of 5863.6 μm^2.The post-simulation results show that the normalized energy deviation（NED） and normalized standard deviation（NSD） are 0.099% and 0.04%, respectively. Compared to existing power balance circuits, the power balance ability of the proposed SRAM has improved 53%.展开更多
A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word ...A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced. Thus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnec- essary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%.展开更多
基金supported by the National Key Laboratory of Materials Behavior and Evaluation Technology in Space Environment(No.6142910220208)National Natural Science Foundation of China(Nos.12105341 and 12035019)the opening fund of Key Laboratory of Silicon Device and Technology,Chinese Academy of Sciences(No.KLSDTJJ2022-3).
文摘This paper explores the impact of back-gate bias (V_(soi)) and supply voltage (V_(DD)) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) under high linear energy transfer heavyion experimentation.The experimental findings demonstrate that applying a negative back-gate bias to NMOS and a positive back-gate bias to PMOS enhances the SEU resistance of SRAM.Specifically,as the back-gate bias for N-type transistors(V_(nsoi)) decreases from 0 to-10 V,the SEU cross section decreases by 93.23%,whereas an increase in the back-gate bias for P-type transistors (V_(psoi)) from 0 to 10 V correlates with an 83.7%reduction in SEU cross section.Furthermore,a significant increase in the SEU cross section was observed with increase in supply voltage,as evidenced by a 159%surge at V_(DD)=1.98 V compared with the nominal voltage of 1.8 V.To explore the physical mechanisms underlying these experimental data,we analyzed the dependence of the critical charge of the circuit and the collected charge on the bias voltage by simulating SEUs using technology computer-aided design.
文摘In recent years,carbon nanotube field effect transistor(CNTFET)has become an attractive alternative to silicon for designing high-performance,highly stable,and low-power static random access memory(SRAM).SRAM serves as a cache memory in computers and many portable devices.Carbon nanotubes(CNTs),because of their exceptional transport capabilities,outstanding thermal conductivities,and impressive current handling capacities,have demonstrated great potential as an alternative device to the standard complementary metal-oxide-semiconductor(CMOS).The SRAM cell design using CNTFET is being compared to SRAM cell designs built using traditional CMOS technology.This paper presents the comprehensive analysis of CMOS&CNTFET based 8T SRAM cell design.Because of the nanoscale size,ballistic transport,and higher carrier mobility of the semiconducting nanotubes in CNTFET,it is integrated into the 8T SRAM cell.The approach incorporates several nonidealities,including the presence of quantum confinement consequences in the peripheral and transverse prescriptions,acoustic and transparent photon diffraction in the region surrounding the channel,as well as the screening effects by parallel CNTs in CNTFETs with multiple CNTs.By incorporating Stanford University CNTFET model in CADENCE(virtuoso)32 nm simulation,we have found that CNTFET SRAM cell is 4 times faster in terms of write/read delay and the write/read power delay product(PDP)value is almost 5 times lower compared to CMOS based SRAM.We have also analyzed the effect of temperature&different tube positions of CNTs on the performance evaluation of the 8T SRAM cell.
基金the National Key Research and Development Program of China(2018YFB2202602)The State Key Program of the National Natural Science Foundation of China(NO.61934005)+1 种基金The National Natural Science Foundation of China(NO.62074001)Joint Funds of the National Natural Science Foundation of China under Grant U19A2074.
文摘Artificial intelligence(AI)processes data-centric applications with minimal effort.However,it poses new challenges to system design in terms of computational speed and energy efficiency.The traditional von Neumann architecture cannot meet the requirements of heavily datacentric applications due to the separation of computation and storage.The emergence of computing inmemory(CIM)is significant in circumventing the von Neumann bottleneck.A commercialized memory architecture,static random-access memory(SRAM),is fast and robust,consumes less power,and is compatible with state-of-the-art technology.This study investigates the research progress of SRAM-based CIM technology in three levels:circuit,function,and application.It also outlines the problems,challenges,and prospects of SRAM-based CIM macros.
基金the National Natural Science Foundation of China(Nos.12035019,11690041,and 11805244).
文摘A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm^(2)).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm^(2)),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm^(2))owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm^(2))),the benefit of the EDAC code is reduced significantly because the multi-bit upset proportion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distributions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some suggestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.
文摘An approach to design small scale CMOS static random access memory (SRAM) is proposed. The design of address decoder, memory cell, and the layout are included. This approach adopts flip-flop array structure. The flip-flops are used as the storage cells and they are stacked to form the whole SRAM module. The word select bit is generated from the address decoder. And one word at a time is selected for reading or writing. The design of the memory core's layout is also discussed since it should be optimized to save area and also should be convenient for realization. It's a full-custom layout. The address decoder is composed of combinational logic circuit and its layout is also designed as a full-custom layout. With all these modules, the integral structure of the SRAM is carried out.
基金Projects(60873016, 61170083) supported by the National Natural Science Foundation of ChinaProject(20114307110001) supported by the Doctoral Fund of Ministry of Education of China
文摘A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM). The experiment results show that PBTI has significant influence on the read and write operations of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 106 s working time. Then, a circuit level simulation was used to verify the assumption of the SPAP model, and finally the statistic data of CPU2000 benchmarks show that the proposed model has a reduction of 3.85% for estimation of the SNM degradation after 106 s working time compared with previous work.
基金Supported by the National High Technology and Development Program of China(2013AA1548)
文摘An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.
基金supported by the National Natural Science Foundation of China(Nos.12105341 and 12035019)the opening fund of Key Laboratory of Silicon Device and Technology,Chinese Academy of Sciences(No.KLSDTJJ2022-3).
文摘The 28 nm process has a high cost-performance ratio and has gradually become the standard for the field of radiation-hardened devices.However,owing to the minimum physical gate length of only 35 nm,the physical area of a standard 6T SRAM unit is approximately 0.16μm^(2),resulting in a significant enhancement of multi-cell charge-sharing effects.Multiple-cell upsets(MCUs)have become the primary physical mechanism behind single-event upsets(SEUs)in advanced nanometer node devices.The range of ionization track effects increases with higher ion energies,and spacecraft in orbit primarily experience SEUs caused by high-energy ions.However,ground accelerator experiments have mainly obtained low-energy ion irradiation data.Therefore,the impact of ion energy on the SEU cross section,charge collection mechanisms,and MCU patterns and quantities in advanced nanometer devices remains unclear.In this study,based on the experimental platform of the Heavy Ion Research Facility in Lanzhou,low-and high-energy heavy-ion beams were used to study the SEUs of 28 nm SRAM devices.The influence of ion energy on the charge collection processes of small-sensitive-volume devices,MCU patterns,and upset cross sections was obtained,and the applicable range of the inverse cosine law was clarified.The findings of this study are an important guide for the accurate evaluation of SEUs in advanced nanometer devices and for the development of radiation-hardening techniques.
基金Project supported by the National Natural Science Foundation of China(Grant No.U1532261)
文摘The pattern dependence in synergistic effects was studied in a 0.18 μm static random access memory（SRAM） circuit.Experiments were performed under two SEU test environments：3 Me V protons and heavy ions.Measured results show different trends.In heavy ion SEU test,the degradation in the peripheral circuitry also existed because the measured SEU cross section decreased regardless of the patterns written to the SRAM array.TCAD simulation was performed.TIDinduced degradation in n MOSFETs mainly induced the imprint effect in the SRAM cell,which is consistent with the measured results under the proton environment,but cannot explain the phenomena observed under heavy ion environment.A possible explanation could be the contribution from the radiation-induced GIDL in pMOSFETs.
基金fundings from the National Natural Science Foundation of China(Nos.62274013 and 92163206)the National Key Research and Development Program of China(No.2023YFB3405600)Science Fund for Creative Research Groups of the National Natural Science Foundation of China(No.12321004)。
文摘Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the evolution of M3D integration from traditional bulk semiconductors to low-dimensional materials like two-dimensioanl(2D)transition metal dichalcogenides(TMDCs)and carbon nanotubes(CNTs).Key applications include logic circuits,static random access memory(SRAM),resistive random access memory(RRAM),sensors,optoelectronics,and artificial intelligence(AI)processing.M3D integration enhances device performance by reducing footprint,improving power efficiency,and alleviating the von Neumann bottleneck.The integration of 2D materials in M3D structures demonstrates significant advancements in terms of scalability,energy efficiency,and functional diversity.Challenges in manufacturing and scaling are discussed,along with prospects for future research directions.Overall,the M3D integration with low-dimensional materials presents a promising pathway for the development of next-generation electronic devices and systems.
基金supported by the National Natural Science Foundation of China(Grant No.61504169)the Preliminary Research Program of National University of Defense Technology of China(Grant No.0100066314001)
文摘In this paper, the characterization of single event multiple cell upsets(MCUs) in a custom SRAM is performed in a 65 nm triple-well CMOS technology, and O(linear energy transfer(LET) = 3.1 Me V cm2/mg), Ti(LET = 22.2 Me V cm2/mg) and Ge(LET = 37.4 Me V cm2/mg) particles are employed. The experimental results show that the percentage of MCU events in total upset events is 71.11%, 83.47% and 85.53% at O, Ti and Ge exposures. Moreover, due to the vertical well isolation layout, 100%(O), 100%(Ti) and 98.11%(Ge) MCU cluster just present at one or two adjacent columns, but there are still 4 cell upsets in one MCU cluster appearing on the same word wire. The characterization indicates that MCUs have become the main source of soft errors in SRAM, and even though combining the storage array interleaving distance(ID) scheme with the error detection and correction(EDAC) technique, the MCUs cannot be completely eliminated, new radiation hardened by design techniques still need to be further studied.
基金Project supported by the Zhejiang Provincial Natural Science Foundation of China(No.LQ14F040001)the National Natural Science Foundation of China(Nos.61274132,61234002)the K.C.Wong Magna Fund in Ningbo University,China
文摘A power balance static random-access memory（SRAM） for resistance to differential power analysis（DPA） is proposed. In the proposed design, the switch power consumption and short-circuit power consumption are balanced by discharging and pre-charging the key nodes of the output circuit and adding an additional shortcircuit current path. Thus, the power consumption is constant in every read cycle. As a result, the DPA-resistant ability of the SRAM is improved. In 65 nm CMOS technology, the power balance SRAM is fully custom designed with a layout area of 5863.6 μm^2.The post-simulation results show that the normalized energy deviation（NED） and normalized standard deviation（NSD） are 0.099% and 0.04%, respectively. Compared to existing power balance circuits, the power balance ability of the proposed SRAM has improved 53%.
基金Project supported by the Zhejiang Provincial Natural Science Foundation of China(No.LQ14F040001)the National Natural Science Foundation of China(Nos.61274132,61234002,61474068)the K.C.Wong Magna Fund in Ningbo University
文摘A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced. Thus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnec- essary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%.
