基于系统级封装(System in a Package, SiP)技术的SRAM型FPGA微系统广泛应用于航天领域。由于微系统复杂的封装结构,限制了大多数传统失效分析设备与分析方式的应用。针对微系统器件的故障诊断困难、测试流程复杂等可靠性问题,开展了常...基于系统级封装(System in a Package, SiP)技术的SRAM型FPGA微系统广泛应用于航天领域。由于微系统复杂的封装结构,限制了大多数传统失效分析设备与分析方式的应用。针对微系统器件的故障诊断困难、测试流程复杂等可靠性问题,开展了常见故障分析研究。对SRAM配置固有缺陷和FPGA内部配置刷新电路异常等典型故障的产生机理进行了深入分析和总结。结合理论分析和问题现象,提出了配置位回读校验测试及比对、辅助电源VCC, AUX电流参数一致性控制等测试筛选方法,有效提升了测试覆盖性。利用相应测试手段和数据分析方法,可精准定位失效机理与失效部位,对后续宇航用SRAM型FPGA微系统应用及筛选有重要意义。展开更多
This paper explores the impact of back-gate bias (V_(soi)) and supply voltage (V_(DD)) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) unde...This paper explores the impact of back-gate bias (V_(soi)) and supply voltage (V_(DD)) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) under high linear energy transfer heavyion experimentation.The experimental findings demonstrate that applying a negative back-gate bias to NMOS and a positive back-gate bias to PMOS enhances the SEU resistance of SRAM.Specifically,as the back-gate bias for N-type transistors(V_(nsoi)) decreases from 0 to-10 V,the SEU cross section decreases by 93.23%,whereas an increase in the back-gate bias for P-type transistors (V_(psoi)) from 0 to 10 V correlates with an 83.7%reduction in SEU cross section.Furthermore,a significant increase in the SEU cross section was observed with increase in supply voltage,as evidenced by a 159%surge at V_(DD)=1.98 V compared with the nominal voltage of 1.8 V.To explore the physical mechanisms underlying these experimental data,we analyzed the dependence of the critical charge of the circuit and the collected charge on the bias voltage by simulating SEUs using technology computer-aided design.展开更多
In recent years,carbon nanotube field effect transistor(CNTFET)has become an attractive alternative to silicon for designing high-performance,highly stable,and low-power static random access memory(SRAM).SRAM serves a...In recent years,carbon nanotube field effect transistor(CNTFET)has become an attractive alternative to silicon for designing high-performance,highly stable,and low-power static random access memory(SRAM).SRAM serves as a cache memory in computers and many portable devices.Carbon nanotubes(CNTs),because of their exceptional transport capabilities,outstanding thermal conductivities,and impressive current handling capacities,have demonstrated great potential as an alternative device to the standard complementary metal-oxide-semiconductor(CMOS).The SRAM cell design using CNTFET is being compared to SRAM cell designs built using traditional CMOS technology.This paper presents the comprehensive analysis of CMOS&CNTFET based 8T SRAM cell design.Because of the nanoscale size,ballistic transport,and higher carrier mobility of the semiconducting nanotubes in CNTFET,it is integrated into the 8T SRAM cell.The approach incorporates several nonidealities,including the presence of quantum confinement consequences in the peripheral and transverse prescriptions,acoustic and transparent photon diffraction in the region surrounding the channel,as well as the screening effects by parallel CNTs in CNTFETs with multiple CNTs.By incorporating Stanford University CNTFET model in CADENCE(virtuoso)32 nm simulation,we have found that CNTFET SRAM cell is 4 times faster in terms of write/read delay and the write/read power delay product(PDP)value is almost 5 times lower compared to CMOS based SRAM.We have also analyzed the effect of temperature&different tube positions of CNTs on the performance evaluation of the 8T SRAM cell.展开更多
The integration of artificial intelligence(AI)with satellite technology is ushering in a new era of space exploration,with small satellites playing a pivotal role in advancing this field.However,the deployment of mach...The integration of artificial intelligence(AI)with satellite technology is ushering in a new era of space exploration,with small satellites playing a pivotal role in advancing this field.However,the deployment of machine learning(ML)models in space faces distinct challenges,such as single event upsets(SEUs),which are triggered by space radiation and can corrupt the outputs of neural networks.To defend against this threat,we investigate laser-based fault injection techniques on 55-nm SRAM cells,aiming to explore the impact of SEUs on neural network performance.In this paper,we propose a novel solution in the form of Bin-DNCNN,a binary neural network(BNN)-based model that significantly enhances robustness to radiation-induced faults.We conduct experiments to evaluate the denoising effectiveness of different neural network architectures,comparing their resilience to weight errors before and after fault injections.Our experimental results demonstrate that binary neural networks(BNNs)exhibit superior robustness to weight errors compared to traditional deep neural networks(DNNs),making them a promising candidate for spaceborne AI applications.展开更多
文摘基于系统级封装(System in a Package, SiP)技术的SRAM型FPGA微系统广泛应用于航天领域。由于微系统复杂的封装结构,限制了大多数传统失效分析设备与分析方式的应用。针对微系统器件的故障诊断困难、测试流程复杂等可靠性问题,开展了常见故障分析研究。对SRAM配置固有缺陷和FPGA内部配置刷新电路异常等典型故障的产生机理进行了深入分析和总结。结合理论分析和问题现象,提出了配置位回读校验测试及比对、辅助电源VCC, AUX电流参数一致性控制等测试筛选方法,有效提升了测试覆盖性。利用相应测试手段和数据分析方法,可精准定位失效机理与失效部位,对后续宇航用SRAM型FPGA微系统应用及筛选有重要意义。
基金supported by the National Key Laboratory of Materials Behavior and Evaluation Technology in Space Environment(No.6142910220208)National Natural Science Foundation of China(Nos.12105341 and 12035019)the opening fund of Key Laboratory of Silicon Device and Technology,Chinese Academy of Sciences(No.KLSDTJJ2022-3).
文摘This paper explores the impact of back-gate bias (V_(soi)) and supply voltage (V_(DD)) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) under high linear energy transfer heavyion experimentation.The experimental findings demonstrate that applying a negative back-gate bias to NMOS and a positive back-gate bias to PMOS enhances the SEU resistance of SRAM.Specifically,as the back-gate bias for N-type transistors(V_(nsoi)) decreases from 0 to-10 V,the SEU cross section decreases by 93.23%,whereas an increase in the back-gate bias for P-type transistors (V_(psoi)) from 0 to 10 V correlates with an 83.7%reduction in SEU cross section.Furthermore,a significant increase in the SEU cross section was observed with increase in supply voltage,as evidenced by a 159%surge at V_(DD)=1.98 V compared with the nominal voltage of 1.8 V.To explore the physical mechanisms underlying these experimental data,we analyzed the dependence of the critical charge of the circuit and the collected charge on the bias voltage by simulating SEUs using technology computer-aided design.
文摘In recent years,carbon nanotube field effect transistor(CNTFET)has become an attractive alternative to silicon for designing high-performance,highly stable,and low-power static random access memory(SRAM).SRAM serves as a cache memory in computers and many portable devices.Carbon nanotubes(CNTs),because of their exceptional transport capabilities,outstanding thermal conductivities,and impressive current handling capacities,have demonstrated great potential as an alternative device to the standard complementary metal-oxide-semiconductor(CMOS).The SRAM cell design using CNTFET is being compared to SRAM cell designs built using traditional CMOS technology.This paper presents the comprehensive analysis of CMOS&CNTFET based 8T SRAM cell design.Because of the nanoscale size,ballistic transport,and higher carrier mobility of the semiconducting nanotubes in CNTFET,it is integrated into the 8T SRAM cell.The approach incorporates several nonidealities,including the presence of quantum confinement consequences in the peripheral and transverse prescriptions,acoustic and transparent photon diffraction in the region surrounding the channel,as well as the screening effects by parallel CNTs in CNTFETs with multiple CNTs.By incorporating Stanford University CNTFET model in CADENCE(virtuoso)32 nm simulation,we have found that CNTFET SRAM cell is 4 times faster in terms of write/read delay and the write/read power delay product(PDP)value is almost 5 times lower compared to CMOS based SRAM.We have also analyzed the effect of temperature&different tube positions of CNTs on the performance evaluation of the 8T SRAM cell.
文摘The integration of artificial intelligence(AI)with satellite technology is ushering in a new era of space exploration,with small satellites playing a pivotal role in advancing this field.However,the deployment of machine learning(ML)models in space faces distinct challenges,such as single event upsets(SEUs),which are triggered by space radiation and can corrupt the outputs of neural networks.To defend against this threat,we investigate laser-based fault injection techniques on 55-nm SRAM cells,aiming to explore the impact of SEUs on neural network performance.In this paper,we propose a novel solution in the form of Bin-DNCNN,a binary neural network(BNN)-based model that significantly enhances robustness to radiation-induced faults.We conduct experiments to evaluate the denoising effectiveness of different neural network architectures,comparing their resilience to weight errors before and after fault injections.Our experimental results demonstrate that binary neural networks(BNNs)exhibit superior robustness to weight errors compared to traditional deep neural networks(DNNs),making them a promising candidate for spaceborne AI applications.
