SPHINCS+是一种无状态的数字签名算法.2022年11月,美国国家标准与技术研究院(NIST)宣布SPHINCS+成为即将被标准化的后量子数字签名算法,目前已进入具体参数选取的讨论阶段.SPHINCS+的安全性仅依赖于其所使用的杂凑函数的抗某种变体的(第...SPHINCS+是一种无状态的数字签名算法.2022年11月,美国国家标准与技术研究院(NIST)宣布SPHINCS+成为即将被标准化的后量子数字签名算法,目前已进入具体参数选取的讨论阶段.SPHINCS+的安全性仅依赖于其所使用的杂凑函数的抗某种变体的(第二)原像攻击的强度,从安全性角度看,基于杂凑函数的数字签名方案是最保守的设计.在第四届NIST后量子密码标准化会议中,NIST后量子密码(NIST PQC)团队Dustin Moody在他的报告“NIST PQC:Looking into the future”中指出了选择SPHINCS+的原因:坚实的安全性以及其基于与格密码不同的安全性假设.本文利用杂凑函数SM3实例化SPHINCS+,给出了2组达到NIST后量子密码算法征集文档(NIST PQC CFP)中第1安全等级的参数实例,并进行了初步的性能测试.展开更多
SPHINCS+is a hash-based digital signature scheme that has been selected for post-quantum cryptography(PQC)standardization announced by the U.S.National Institute of Standards and Technology(NIST)in 2022.Although SPHIN...SPHINCS+is a hash-based digital signature scheme that has been selected for post-quantum cryptography(PQC)standardization announced by the U.S.National Institute of Standards and Technology(NIST)in 2022.Although SPHINCS+offers significant security against quantum attacks,its relatively slow computation times present a major obstacle to its practical deployment.To address this challenge,improving the computational efficiency of SPHINCS+becomes a critical task.The cryptographic operations in SPHINCS+rely on tweakable hash functions,with various hash algorithms available for selection.Among these,SHA-3 stands out as a widely adopted and NIST-standardized hash function,making it a preferred choice for implementation in SPHINCS+.In this work,we propose a dedicated coprocessor that integrates a SHA-3 accelerator along with its associated peripheral structure.This coprocessor is designed to extend the RISC-V instruction set by incorporating seven custom instructions,enabling efficient software-hardware co-acceleration.Furthermore,we investigate the parallelizable components within SPHINCS+,specifically the FORS and WOTS+Algorithms,to identify means for optimization.By leveraging thread-level parallelism through multi-core programming,we achieve significant improvements in performance.To validate the design,synthesis is performed using TSMC 28-nm CMOS technology at 800 MHz.Compared to the benchmark results from the ARM Cortex-M4 processor,our approach achieves an impressive 23.1×speedup in the overall single-core performance of SPHINCS+,with an additional 3.4×speedup for the verification process by utilizing multi-core acceleration.展开更多
文摘SPHINCS+是一种无状态的数字签名算法.2022年11月,美国国家标准与技术研究院(NIST)宣布SPHINCS+成为即将被标准化的后量子数字签名算法,目前已进入具体参数选取的讨论阶段.SPHINCS+的安全性仅依赖于其所使用的杂凑函数的抗某种变体的(第二)原像攻击的强度,从安全性角度看,基于杂凑函数的数字签名方案是最保守的设计.在第四届NIST后量子密码标准化会议中,NIST后量子密码(NIST PQC)团队Dustin Moody在他的报告“NIST PQC:Looking into the future”中指出了选择SPHINCS+的原因:坚实的安全性以及其基于与格密码不同的安全性假设.本文利用杂凑函数SM3实例化SPHINCS+,给出了2组达到NIST后量子密码算法征集文档(NIST PQC CFP)中第1安全等级的参数实例,并进行了初步的性能测试.
基金supported by the National Natural Science Foundation of China under Grant 62234008Grant 61934002.
文摘SPHINCS+is a hash-based digital signature scheme that has been selected for post-quantum cryptography(PQC)standardization announced by the U.S.National Institute of Standards and Technology(NIST)in 2022.Although SPHINCS+offers significant security against quantum attacks,its relatively slow computation times present a major obstacle to its practical deployment.To address this challenge,improving the computational efficiency of SPHINCS+becomes a critical task.The cryptographic operations in SPHINCS+rely on tweakable hash functions,with various hash algorithms available for selection.Among these,SHA-3 stands out as a widely adopted and NIST-standardized hash function,making it a preferred choice for implementation in SPHINCS+.In this work,we propose a dedicated coprocessor that integrates a SHA-3 accelerator along with its associated peripheral structure.This coprocessor is designed to extend the RISC-V instruction set by incorporating seven custom instructions,enabling efficient software-hardware co-acceleration.Furthermore,we investigate the parallelizable components within SPHINCS+,specifically the FORS and WOTS+Algorithms,to identify means for optimization.By leveraging thread-level parallelism through multi-core programming,we achieve significant improvements in performance.To validate the design,synthesis is performed using TSMC 28-nm CMOS technology at 800 MHz.Compared to the benchmark results from the ARM Cortex-M4 processor,our approach achieves an impressive 23.1×speedup in the overall single-core performance of SPHINCS+,with an additional 3.4×speedup for the verification process by utilizing multi-core acceleration.
