为了在薄埋氧层SOI衬底上实现超高耐压LDMOS铺平道路,提出了一种具有P埋层(BPL)的薄埋氧层SOI LDMOS结构,耐压1200V以上。该BPL SOI LDMOS在传统SOI LDMOS的埋氧层和N型漂移区之间引入了一个P型埋层。当器件正向截止时,N型漂移区与P埋...为了在薄埋氧层SOI衬底上实现超高耐压LDMOS铺平道路,提出了一种具有P埋层(BPL)的薄埋氧层SOI LDMOS结构,耐压1200V以上。该BPL SOI LDMOS在传统SOI LDMOS的埋氧层和N型漂移区之间引入了一个P型埋层。当器件正向截止时,N型漂移区与P埋层之间的反偏PN结将承担器件的绝大部分纵向压降。采用2维数值仿真工具Silvaco TCAD对BPL SOI LDMOS进行虚拟制造和器件仿真,结果表明该结构采用适当的参数既能实现1 280 V的耐压,将BOL减薄到几百纳米以下又可以改善其热特性。展开更多
为提升SRAM型FPGA电路块存储器和配置存储器抗单粒子翻转性能,本文提出一种脉冲屏蔽SRAM单元结构。该结构通过在标准的六管单元中加入延迟结构,增大单元对单粒子事件响应时间,实现对粒子入射产生的脉冲电流屏蔽作用。以64k SRAM作为验...为提升SRAM型FPGA电路块存储器和配置存储器抗单粒子翻转性能,本文提出一种脉冲屏蔽SRAM单元结构。该结构通过在标准的六管单元中加入延迟结构,增大单元对单粒子事件响应时间,实现对粒子入射产生的脉冲电流屏蔽作用。以64k SRAM作为验证电路进行单粒子翻转性能对比,电路的抗单粒子翻转阈值由采用标准六管单元的抗单粒子翻转阈值大于25 Me V·cm2·mg-1提升至大于45 Me V·cm2·mg-1,加固单元面积较标准六管单元增大约21.3%。30万门级抗辐照FPGA电路通过脉冲屏蔽单元结合抗辐照SOI工艺实现,其抗辐照指标分别为:抗单粒子翻转阈值大于37.3 Me V·cm2·mg-1,抗单粒子锁定阈值大于99.8 Me V·cm2·mg-1,抗电离总剂量能力大于200 krad(Si)。展开更多
基于简正模式的MEMS超声分离器对分离腔的侧壁垂直度、深度均匀性以及表面平整度等要求较高,结合IC工艺重点探讨、研究了超声分离器腔体制作方法。提出将SOI(silicon on insulator)片作为刻蚀基底,采用等离子体干法刻蚀、硅/玻璃键合以...基于简正模式的MEMS超声分离器对分离腔的侧壁垂直度、深度均匀性以及表面平整度等要求较高,结合IC工艺重点探讨、研究了超声分离器腔体制作方法。提出将SOI(silicon on insulator)片作为刻蚀基底,采用等离子体干法刻蚀、硅/玻璃键合以及激光热加工等技术制备分离器,成功制备出腔体深度分别为137μm和200μm的分离器,腔体深度误差均在±2μm以内,腔体表面粗糙度Ra<10 nm,腔体侧壁垂直度达83°。为MEMS超声分离器的制备提供了一种简便、高效的工艺方法。展开更多
Silicon micro-ring resonators （MRRs） are compact and versatile devices whose periodic frequency response can be exploited for a wide range of applications. In this paper, we review our recent work on linear all-opti...Silicon micro-ring resonators （MRRs） are compact and versatile devices whose periodic frequency response can be exploited for a wide range of applications. In this paper, we review our recent work on linear all-optical signal processing applications using silicon MRRs as passive filters. We focus on applications such as modulation format conversion, differential phase-shift keying （DPSK） demodulation, modulation speed enhancement of directly modulated lasers （DMLs）, and monocycle pulse generation. The possibility to implement polarization diversity circuits, which reduce the polarization dependence of standard silicon MRRs, is illustrated on the particular example of DPSK demodulation.展开更多
The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons： one is over-etchi...The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons： one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon comer of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon comers at their weak points, increasing the applied voltage by 15-20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundry＇s 0.5-μm HV SOI technology.展开更多
基金Innovative Scientific Research Project for Graduate Student of Zhejiang Province(YK2010059)Project supported by the Science and Technology development plan of Zhejiang Province(2006AA09Z228)
文摘为了在薄埋氧层SOI衬底上实现超高耐压LDMOS铺平道路,提出了一种具有P埋层(BPL)的薄埋氧层SOI LDMOS结构,耐压1200V以上。该BPL SOI LDMOS在传统SOI LDMOS的埋氧层和N型漂移区之间引入了一个P型埋层。当器件正向截止时,N型漂移区与P埋层之间的反偏PN结将承担器件的绝大部分纵向压降。采用2维数值仿真工具Silvaco TCAD对BPL SOI LDMOS进行虚拟制造和器件仿真,结果表明该结构采用适当的参数既能实现1 280 V的耐压,将BOL减薄到几百纳米以下又可以改善其热特性。
文摘为提升SRAM型FPGA电路块存储器和配置存储器抗单粒子翻转性能,本文提出一种脉冲屏蔽SRAM单元结构。该结构通过在标准的六管单元中加入延迟结构,增大单元对单粒子事件响应时间,实现对粒子入射产生的脉冲电流屏蔽作用。以64k SRAM作为验证电路进行单粒子翻转性能对比,电路的抗单粒子翻转阈值由采用标准六管单元的抗单粒子翻转阈值大于25 Me V·cm2·mg-1提升至大于45 Me V·cm2·mg-1,加固单元面积较标准六管单元增大约21.3%。30万门级抗辐照FPGA电路通过脉冲屏蔽单元结合抗辐照SOI工艺实现,其抗辐照指标分别为:抗单粒子翻转阈值大于37.3 Me V·cm2·mg-1,抗单粒子锁定阈值大于99.8 Me V·cm2·mg-1,抗电离总剂量能力大于200 krad(Si)。
文摘基于简正模式的MEMS超声分离器对分离腔的侧壁垂直度、深度均匀性以及表面平整度等要求较高,结合IC工艺重点探讨、研究了超声分离器腔体制作方法。提出将SOI(silicon on insulator)片作为刻蚀基底,采用等离子体干法刻蚀、硅/玻璃键合以及激光热加工等技术制备分离器,成功制备出腔体深度分别为137μm和200μm的分离器,腔体深度误差均在±2μm以内,腔体表面粗糙度Ra<10 nm,腔体侧壁垂直度达83°。为MEMS超声分离器的制备提供了一种简便、高效的工艺方法。
文摘Silicon micro-ring resonators （MRRs） are compact and versatile devices whose periodic frequency response can be exploited for a wide range of applications. In this paper, we review our recent work on linear all-optical signal processing applications using silicon MRRs as passive filters. We focus on applications such as modulation format conversion, differential phase-shift keying （DPSK） demodulation, modulation speed enhancement of directly modulated lasers （DMLs）, and monocycle pulse generation. The possibility to implement polarization diversity circuits, which reduce the polarization dependence of standard silicon MRRs, is illustrated on the particular example of DPSK demodulation.
文摘The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons： one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon comer of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon comers at their weak points, increasing the applied voltage by 15-20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundry＇s 0.5-μm HV SOI technology.
