提出一种新型的基于FPGA硬件实现的SMS4分组密码算法电路设计。相对于常用的流水线设计方法和迭代设计方法,此设计将流水线和迭代运算相结合,结合了前者较高处理速度和后者较小实现面积的优点,达到了较好的性能,对WLAN商用密码算法的FPG...提出一种新型的基于FPGA硬件实现的SMS4分组密码算法电路设计。相对于常用的流水线设计方法和迭代设计方法,此设计将流水线和迭代运算相结合,结合了前者较高处理速度和后者较小实现面积的优点,达到了较好的性能,对WLAN商用密码算法的FPGA硬件实现有参考意义。通过Quartus II 8.0软件时序仿真验证了此设计的正确性,并使用以Cyclone II FPGA芯片为核心的DE2开发板验证了此设计的可实现性。展开更多
文章在分析SMS4原理的基础上提出了一种基于单轮循环结构的SMS4加密方案,通过复用单一的加密单元,经过32次循环迭代完成加密,大大减少了硬件资源的使用。该设计的开发平台是Altera公司的Quartus II 9.0,使用的FPGA(Field-Programmable G...文章在分析SMS4原理的基础上提出了一种基于单轮循环结构的SMS4加密方案,通过复用单一的加密单元,经过32次循环迭代完成加密,大大减少了硬件资源的使用。该设计的开发平台是Altera公司的Quartus II 9.0,使用的FPGA(Field-Programmable Gate Array)开发板是Cyclone II EP2C8Q208C8。运行结果表明,SMS4加密芯片使用了5 268个逻辑单元和139 264位存储器资源,系统的时钟频率可以达到51.35 MHz,信息加/解密的峰值速度为3.2Gb/s,系统功耗为132.30 m W。展开更多
硬件实现的SMS4加密算法计算过程中容易出现故障,为防止攻击者利用故障信息进行故障攻击从而破解SMS4算法,提出一种针对SMS4算法的故障检测方案。该方案首先分析了硬件实现的SMS4算法出现故障的位置及其影响,然后在关键路径上建立了3个...硬件实现的SMS4加密算法计算过程中容易出现故障,为防止攻击者利用故障信息进行故障攻击从而破解SMS4算法,提出一种针对SMS4算法的故障检测方案。该方案首先分析了硬件实现的SMS4算法出现故障的位置及其影响,然后在关键路径上建立了3个检测点,通过实时监测检测点来定位算法执行过程中出现的故障。一旦成功检测到故障,立即重新执行算法以保证攻击者难以获取有效的故障信息。将提出的方案和原无故障检测的算法分别在Xilinx公司的Virtex-7和Altera公司的Cyclone II EP2C35F76C6两个现场可编程门阵列(FPGA)上综合实现,在Virtex-7上,提出的带故障检测的方案比原算法占用逻辑资源增加30%,吞吐量相当;在EP2C35F76C6上比原算法增加0.1%的硬件资源,吞吐量达到原来的93%。实验结果表明,在尽量不影响吞吐量的前提下,提出的方案占用硬件资源小,并且可以有效地检测出故障,从而避免SMS4算法受到故障攻击。展开更多
SM4 is a block cipher algorithm among Chinese commer-cial cryptographic algorithms,which is advanced in terms of efficiency and theoretical security and has become national and international stan-dards successively.Howe...SM4 is a block cipher algorithm among Chinese commer-cial cryptographic algorithms,which is advanced in terms of efficiency and theoretical security and has become national and international stan-dards successively.However,existing literature shows that SM4 was not designed with an emphasis on key storage,which means that in today’s world where a single trusted hardware device with the built-in key faces challenges such as vulnerability,high cost,and unreliability,the usabil-ity of SM4 may be limited.Therefore,this paper proposes an imple-mentation scheme for SM4 based on secure multi-party computation(MPC)technology.The scheme involves dispensing the key among mul-tiple users’devices in a distributed manner,and when using the SM4 algorithm for encryption,multiple users perform joint computation with-out opening the full key.Specifically,this paper employs the MP-SPDZ framework,which satisfies security requirements in the presence of a dishonest majority of active adversaries.In view of the fact that this framework can only perform basic linear operations such as addition and multiplication,this paper focuses on the algebraic analysis of Sbox,which is the only non-linear component in SM4,and reconstructs it using the bit decomposition method.Furthermore,this paper demonstrates the conversion between the SM4-Sboxfield GF(28)and the SPDZ parame-terfield GF(240)through the isomorphic mapping,making it possible to perform joint calculations throughout the entire SM4 algorithm.Com-plexity analysis shows that this scheme has advantages in terms of data storage and communication volume,reaching a level of usability.展开更多
文摘提出一种新型的基于FPGA硬件实现的SMS4分组密码算法电路设计。相对于常用的流水线设计方法和迭代设计方法,此设计将流水线和迭代运算相结合,结合了前者较高处理速度和后者较小实现面积的优点,达到了较好的性能,对WLAN商用密码算法的FPGA硬件实现有参考意义。通过Quartus II 8.0软件时序仿真验证了此设计的正确性,并使用以Cyclone II FPGA芯片为核心的DE2开发板验证了此设计的可实现性。
文摘文章在分析SMS4原理的基础上提出了一种基于单轮循环结构的SMS4加密方案,通过复用单一的加密单元,经过32次循环迭代完成加密,大大减少了硬件资源的使用。该设计的开发平台是Altera公司的Quartus II 9.0,使用的FPGA(Field-Programmable Gate Array)开发板是Cyclone II EP2C8Q208C8。运行结果表明,SMS4加密芯片使用了5 268个逻辑单元和139 264位存储器资源,系统的时钟频率可以达到51.35 MHz,信息加/解密的峰值速度为3.2Gb/s,系统功耗为132.30 m W。
文摘硬件实现的SMS4加密算法计算过程中容易出现故障,为防止攻击者利用故障信息进行故障攻击从而破解SMS4算法,提出一种针对SMS4算法的故障检测方案。该方案首先分析了硬件实现的SMS4算法出现故障的位置及其影响,然后在关键路径上建立了3个检测点,通过实时监测检测点来定位算法执行过程中出现的故障。一旦成功检测到故障,立即重新执行算法以保证攻击者难以获取有效的故障信息。将提出的方案和原无故障检测的算法分别在Xilinx公司的Virtex-7和Altera公司的Cyclone II EP2C35F76C6两个现场可编程门阵列(FPGA)上综合实现,在Virtex-7上,提出的带故障检测的方案比原算法占用逻辑资源增加30%,吞吐量相当;在EP2C35F76C6上比原算法增加0.1%的硬件资源,吞吐量达到原来的93%。实验结果表明,在尽量不影响吞吐量的前提下,提出的方案占用硬件资源小,并且可以有效地检测出故障,从而避免SMS4算法受到故障攻击。
基金Supported by the National Natural Science Foundation of China under Grant No.61907042Beijing Natural Science Foundation under Grant No.4194090.
文摘SM4 is a block cipher algorithm among Chinese commer-cial cryptographic algorithms,which is advanced in terms of efficiency and theoretical security and has become national and international stan-dards successively.However,existing literature shows that SM4 was not designed with an emphasis on key storage,which means that in today’s world where a single trusted hardware device with the built-in key faces challenges such as vulnerability,high cost,and unreliability,the usabil-ity of SM4 may be limited.Therefore,this paper proposes an imple-mentation scheme for SM4 based on secure multi-party computation(MPC)technology.The scheme involves dispensing the key among mul-tiple users’devices in a distributed manner,and when using the SM4 algorithm for encryption,multiple users perform joint computation with-out opening the full key.Specifically,this paper employs the MP-SPDZ framework,which satisfies security requirements in the presence of a dishonest majority of active adversaries.In view of the fact that this framework can only perform basic linear operations such as addition and multiplication,this paper focuses on the algebraic analysis of Sbox,which is the only non-linear component in SM4,and reconstructs it using the bit decomposition method.Furthermore,this paper demonstrates the conversion between the SM4-Sboxfield GF(28)and the SPDZ parame-terfield GF(240)through the isomorphic mapping,making it possible to perform joint calculations throughout the entire SM4 algorithm.Com-plexity analysis shows that this scheme has advantages in terms of data storage and communication volume,reaching a level of usability.
