The substitution table (S-Box) of Advanced Encryption Standard (AES) and its properties are key elements in cryptanalysis ciphering. We aim here to propose a straightforward method for the non-linear transformation of...The substitution table (S-Box) of Advanced Encryption Standard (AES) and its properties are key elements in cryptanalysis ciphering. We aim here to propose a straightforward method for the non-linear transformation of AES S-Box construction. The method reduces the steps needed to compute the multiplicative inverse, and computes the matrices multiplication used in this transformation, without a need to use the characteristic matrix, and the result is a modern method constructing the S-Box.展开更多
In order to improve the data throughput of the advanced encryption standard （AES） IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline ar...In order to improve the data throughput of the advanced encryption standard （AES） IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline architecture and reconfigurable technology for the design and implementation of the AES IP core is proposed. The encryption and decryption processes of the AES algorithm are achieved in the same process within the mixed pipeline structure. According to the finite field characterizations, the Sbox in the AES algorithm is optimized. ShiftRow and MixColumn, which are the main components in AES round transformation, are optimized with the reconfigurable technology. The design is implemented on the Xilinx Virtex2p xc2vp20-7 field programmable gate array （FPGA） device. It can achieve a data throughput above 2.58 Gbit/s, and it only requires 3 233 slices. Compared with other related designs of AES IP cores on the same device, the proposed design can achieve a tradeoff between speed and area, and obtain satisfactory results in both data throughput and hardware resource consumption.展开更多
Reconfigurable computing has grown to become an important and large field of research, it offers advantages over traditional hardware and software implementations of computational algorithms. The Advanced Encryption S...Reconfigurable computing has grown to become an important and large field of research, it offers advantages over traditional hardware and software implementations of computational algorithms. The Advanced Encryption Standard （AES） algorithm is widely applied in government department and commerce. This paper analyzed the AES algorithms with different cipher keys, adopted a novel key scheduler that generated the round key real-time, proposed a dynamically reconfigurable encryption system which supported the AES algorithm with different cipher keys, and designed the architecture of the reconfigurable system. The dynamically reconfigurable AES system had been realized on FPGA. The result proves that the reconfigurable AES system is flexible, lower cost and high security level.展开更多
With the widespread use of the internet,there is an increasing need to ensure the security and privacy of transmitted data.This has led to an intensified focus on the study of video steganography,which is a technique ...With the widespread use of the internet,there is an increasing need to ensure the security and privacy of transmitted data.This has led to an intensified focus on the study of video steganography,which is a technique that hides data within a video cover to avoid detection.The effectiveness of any steganography method depends on its ability to embed data without altering the original video’s quality while maintaining high efficiency.This paper proposes a new method to video steganography,which involves utilizing a Genetic Algorithm(GA)for identifying the Region of Interest(ROI)in the cover video.The ROI is the area in the video that is the most suitable for data embedding.The secret data is encrypted using the Advanced Encryption Standard(AES),which is a widely accepted encryption standard,before being embedded into the cover video,utilizing up to 10%of the cover video.This process ensures the security and confidentiality of the embedded data.The performance metrics for assessing the proposed method are the Peak Signalto-Noise Ratio(PSNR)and the encoding and decoding time.The results show that the proposed method has a high embedding capacity and efficiency,with a PSNR ranging between 64 and 75 dBs,which indicates that the embedded data is almost indistinguishable from the original video.Additionally,the method can encode and decode data quickly,making it efficient for real-time applications.展开更多
文摘The substitution table (S-Box) of Advanced Encryption Standard (AES) and its properties are key elements in cryptanalysis ciphering. We aim here to propose a straightforward method for the non-linear transformation of AES S-Box construction. The method reduces the steps needed to compute the multiplicative inverse, and computes the matrices multiplication used in this transformation, without a need to use the characteristic matrix, and the result is a modern method constructing the S-Box.
文摘In order to improve the data throughput of the advanced encryption standard （AES） IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline architecture and reconfigurable technology for the design and implementation of the AES IP core is proposed. The encryption and decryption processes of the AES algorithm are achieved in the same process within the mixed pipeline structure. According to the finite field characterizations, the Sbox in the AES algorithm is optimized. ShiftRow and MixColumn, which are the main components in AES round transformation, are optimized with the reconfigurable technology. The design is implemented on the Xilinx Virtex2p xc2vp20-7 field programmable gate array （FPGA） device. It can achieve a data throughput above 2.58 Gbit/s, and it only requires 3 233 slices. Compared with other related designs of AES IP cores on the same device, the proposed design can achieve a tradeoff between speed and area, and obtain satisfactory results in both data throughput and hardware resource consumption.
基金Supported by the National Natural Science Foun-dation of China (60374008)
文摘Reconfigurable computing has grown to become an important and large field of research, it offers advantages over traditional hardware and software implementations of computational algorithms. The Advanced Encryption Standard （AES） algorithm is widely applied in government department and commerce. This paper analyzed the AES algorithms with different cipher keys, adopted a novel key scheduler that generated the round key real-time, proposed a dynamically reconfigurable encryption system which supported the AES algorithm with different cipher keys, and designed the architecture of the reconfigurable system. The dynamically reconfigurable AES system had been realized on FPGA. The result proves that the reconfigurable AES system is flexible, lower cost and high security level.
文摘With the widespread use of the internet,there is an increasing need to ensure the security and privacy of transmitted data.This has led to an intensified focus on the study of video steganography,which is a technique that hides data within a video cover to avoid detection.The effectiveness of any steganography method depends on its ability to embed data without altering the original video’s quality while maintaining high efficiency.This paper proposes a new method to video steganography,which involves utilizing a Genetic Algorithm(GA)for identifying the Region of Interest(ROI)in the cover video.The ROI is the area in the video that is the most suitable for data embedding.The secret data is encrypted using the Advanced Encryption Standard(AES),which is a widely accepted encryption standard,before being embedded into the cover video,utilizing up to 10%of the cover video.This process ensures the security and confidentiality of the embedded data.The performance metrics for assessing the proposed method are the Peak Signalto-Noise Ratio(PSNR)and the encoding and decoding time.The results show that the proposed method has a high embedding capacity and efficiency,with a PSNR ranging between 64 and 75 dBs,which indicates that the embedded data is almost indistinguishable from the original video.Additionally,the method can encode and decode data quickly,making it efficient for real-time applications.
