We present a novel standard convolutional symbols generator(SCSG)block for a multi-parameter reconfigurable Viterbi decoder to optimize resource consumption and adaption of multiple parameters.The SCSG block generates...We present a novel standard convolutional symbols generator(SCSG)block for a multi-parameter reconfigurable Viterbi decoder to optimize resource consumption and adaption of multiple parameters.The SCSG block generates all the states and calculates all the possible standard convolutional symbols corresponding to the states using an iterative approach.The architecture of the Viterbi decoder based on the SCSG reduces resource consumption for recalculating the branch metrics and rearranging the correspondence between branch metrics and transition paths.The proposed architecture supports constraint lengths from 3 to 9,code rates of 1/2,1/3,and 1/4,and fully optional polynomials.The proposed Viterbi decoder has been implemented on the Xilinx XC7VX485T device with a high throughput of about 200 Mbps and a low resource consumption of 162k logic gates.展开更多
基金Project supported by the Natural Science Foundation of Jiangsu Province,China(No.BK20130156)the Summit of the Six Top Talents Program of Jiangsu Province,China(No.2013-DZXX-027)+1 种基金the Fundamental Research Funds for the Central Universities,China(No.JUSRP51510)the Graduate Student Innovation Program for Universities of Jiangsu Province,China(Nos.KYLX15_1192,KYLX16_0776,and SJLX16_0500)
文摘We present a novel standard convolutional symbols generator(SCSG)block for a multi-parameter reconfigurable Viterbi decoder to optimize resource consumption and adaption of multiple parameters.The SCSG block generates all the states and calculates all the possible standard convolutional symbols corresponding to the states using an iterative approach.The architecture of the Viterbi decoder based on the SCSG reduces resource consumption for recalculating the branch metrics and rearranging the correspondence between branch metrics and transition paths.The proposed architecture supports constraint lengths from 3 to 9,code rates of 1/2,1/3,and 1/4,and fully optional polynomials.The proposed Viterbi decoder has been implemented on the Xilinx XC7VX485T device with a high throughput of about 200 Mbps and a low resource consumption of 162k logic gates.
