Novel schemes for a charge sensitive amplifier （CSA） and a CR-（RC）, semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as ...Novel schemes for a charge sensitive amplifier （CSA） and a CR-（RC）, semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as feedback components to reduce noise. Compared with conventional CSA, the input referred equivalent noise charge（ENC） is simulated to be reduced from 5036e to 2381e with a large detector capacitance of 150pF at the cost of 0.5V output swing loss. The CR-（RC）,semi-Gaussian shaper uses MOS transistors in the triode region in series with poly-resistors to compensate process variation without much linearity reduction.展开更多
The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the tradi...The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper, a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 μm complementary metal-oxide-semiconductor transistor （CMOS） technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit （ROIC） with a larger array, such as 320×240 size array.展开更多
Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is ...Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.展开更多
The output of uncooled microbolometer is nonuniform, and the traditional two-point nonuniformity correction method requires a tight restriction on substrate temperature. The circuit proposed by this article can relax ...The output of uncooled microbolometer is nonuniform, and the traditional two-point nonuniformity correction method requires a tight restriction on substrate temperature. The circuit proposed by this article can relax the restriction on the substrate temperature and perform nonuniformity correction when reading out the image signal. The dummy pixels reduce static current. And the Column shared DACs transfer correction data to the gates of MOS transistors and the positive reference edge of amplifier, to control the bias current of detector and dummy one, and set the start point of integration. This circuit has higher sensitivity, wider dynamic range, and frame frequency of more than 30 Hz for 128×128 array. PSPICE simulation results seem that this circuit functions well.展开更多
Presented is a low noise interface circuit that is tuned to the needs of self-assembly monolayers biosensor SoC. The correlated double sampling(CDS) unit of the readout circuit can reduce 1/f noise, KTC noise and fixe...Presented is a low noise interface circuit that is tuned to the needs of self-assembly monolayers biosensor SoC. The correlated double sampling(CDS) unit of the readout circuit can reduce 1/f noise, KTC noise and fixed noise of micro arrays effectively. The circuit is simulated in a 0.6 μm/level 7 standard CMOS process, and the simulated results show the output voltage has a good linearity with the transducing current of the micro arrays. This is a novel circuit including four amplifiers sharing a common half-circuit and the noise reducing CDS unit. It could be widely used for micro array biosensors.展开更多
A novel ultra-low-power readout integrated circuit(ROIC) for 1 024×1 024 ultraviolet(UV) AlGaN focal plane arrays(FPA) with 18 μm-pitch was presented. In order to optimize power consumption for UVFPA readout cir...A novel ultra-low-power readout integrated circuit(ROIC) for 1 024×1 024 ultraviolet(UV) AlGaN focal plane arrays(FPA) with 18 μm-pitch was presented. In order to optimize power consumption for UVFPA readout circuit these methods were adopted, which including single-terminal amplifier under subthreshold region as CTIA amplifier, common current source load for source follow(SF) buffer in column pixels and level shift circuits, and time-sharing tail current source for column buffer. The smallest operational current of CTIA in pixel unit is only 8.5 nA with 3.3 V power supply by using single-terminal amplifier. The ROIC has been fabricated in SMIC 0.18 μm 1P6M mixed signal process and also achieved better performances with the novel design of bias current adjustable. Furthermore, the overall power consumption of the chip is 67.3 mW at 2 MHz in 8-outputs mode by the above methods according to the experimental results.展开更多
A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution inf...A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution infrared focal plane array applications is proposed. The detector bias error in this structure is less than 0.1 mV. The input resistance is ideally zero, which is important to obtain high injection efficiency. Unit-cell occupies 10 μm × 15 μm area and consumes less than 0.4 mW power. Charge storag...展开更多
The development of low-cost,non-enzymatic glucose biosensors is crucial for advancing accessible diabetes management.This paper presents the experimental testing of an extended-gate field-effect transistor(EG-FET)that...The development of low-cost,non-enzymatic glucose biosensors is crucial for advancing accessible diabetes management.This paper presents the experimental testing of an extended-gate field-effect transistor(EG-FET)that uses a gold film as the sensing structure.The system innovatively employs a custom-designed inverting operational amplifier circuit for precise signal acquisition and an Arduino Nano platform for real-time data processing and visualization,eliminating the need for expensive laboratory equipment.At the core of the design is a depletion-mode MOSFET,whose current-voltage properties were characterized.The function of the sensor was demonstrated by testing its response to phosphate-buffered saline containing glucose at different concentrations.A clear modulation of the drain current in the linear region of the EG-FET was observed,and a preliminary analysis revealed a linear correlation between the output current and glucose concentration,indicating the system’s potential for quantitative detection.This study successfully validates the feasibility of a compact,cost-effective,and non-enzymatic EG-FET biosensing platform,establishing a solid foundation for future development of point-of-care diagnostic devices.展开更多
Abstract： This paper presents a charge-sensitive-amplifier （CSA） based readout circuit for capacitive microelectro-mechanical-system （MEMS） sensors. A continuous-time （CT） readout structure using the chopper te...Abstract： This paper presents a charge-sensitive-amplifier （CSA） based readout circuit for capacitive microelectro-mechanical-system （MEMS） sensors. A continuous-time （CT） readout structure using the chopper technique is adopted to cancel the low frequency noise and improve the resolution of the readout circuits. An operational trans-conductance amplifier （OTA） structure with an auxiliary common-mode-feedback-OTA is proposed in the fully differential CSA to suppress the chopper modulation induced disturbance at the OTA input terminal. An analog temperature compensation method is proposed, which adjusts the chopper signal amplitude with temperature variation to compensate the temperature drift of the CSA readout sensitivity. The chip is designed and implemented in a 0.35μm CMOS process and is 2.1 × 2.1 mm2 in area. The measurement shows that the readout circuit achieves 0.9 aF/√H capacitive resolution, 97 dB dynamic range in 100 Hz signal bandwidth, and 0.8 mV/fF sensitivity with a temperature drift of 35 ppm/℃ after optimized compensation.展开更多
Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end ...Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end circuit design.In this paper,we present a 0.18μm CMOS front-end readout circuit for low noise CdZnTe detectors in tens of pF capacitance.Solutions to the noise and gate leak problems in DSM technologies are discussed in detail.A prototype chip was designed,with a charge sensitive preamplifier,a 4th order semi-Gaussian shaper and several output drivers.Test results show that the chip has an equivalent noise charge of 164 e,without connecting it to a detector,with an integral nonlinearity of<0.21%and differential nonlinearity of<3.75%.展开更多
A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuo...A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuous-time semi-Gaussian filter is chosen to avoid switch noise.The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application.The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology.Test results show the functions of the readout integrated circuit are correct.The equivalent noise charge with no detector connected is 500–700 e in the typical mode,the gain is tunable within 13–130 mV/fC and the peaking time varies from 0.7 to 1.6 μs,in which the average gain is about 20.5 mV/fC,and the linearity reaches 99.2%.展开更多
文摘Novel schemes for a charge sensitive amplifier （CSA） and a CR-（RC）, semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as feedback components to reduce noise. Compared with conventional CSA, the input referred equivalent noise charge（ENC） is simulated to be reduced from 5036e to 2381e with a large detector capacitance of 150pF at the cost of 0.5V output swing loss. The CR-（RC）,semi-Gaussian shaper uses MOS transistors in the triode region in series with poly-resistors to compensate process variation without much linearity reduction.
基金supported by the Fundamental Research Funds for the Central Universities under Grant No. 2009JBM001
文摘The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper, a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 μm complementary metal-oxide-semiconductor transistor （CMOS） technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit （ROIC） with a larger array, such as 320×240 size array.
基金The Natural Science Foundation of Jiangsu Province(No.BK2012559)Qing Lan Project of Jiangsu Province
文摘Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.
基金the National Science Foundation of China (No:60377036).
文摘The output of uncooled microbolometer is nonuniform, and the traditional two-point nonuniformity correction method requires a tight restriction on substrate temperature. The circuit proposed by this article can relax the restriction on the substrate temperature and perform nonuniformity correction when reading out the image signal. The dummy pixels reduce static current. And the Column shared DACs transfer correction data to the gates of MOS transistors and the positive reference edge of amplifier, to control the bias current of detector and dummy one, and set the start point of integration. This circuit has higher sensitivity, wider dynamic range, and frame frequency of more than 30 Hz for 128×128 array. PSPICE simulation results seem that this circuit functions well.
基金Natural Science Foundation Project of CQ(2007BB2176)
文摘Presented is a low noise interface circuit that is tuned to the needs of self-assembly monolayers biosensor SoC. The correlated double sampling(CDS) unit of the readout circuit can reduce 1/f noise, KTC noise and fixed noise of micro arrays effectively. The circuit is simulated in a 0.6 μm/level 7 standard CMOS process, and the simulated results show the output voltage has a good linearity with the transducing current of the micro arrays. This is a novel circuit including four amplifiers sharing a common half-circuit and the noise reducing CDS unit. It could be widely used for micro array biosensors.
文摘A novel ultra-low-power readout integrated circuit(ROIC) for 1 024×1 024 ultraviolet(UV) AlGaN focal plane arrays(FPA) with 18 μm-pitch was presented. In order to optimize power consumption for UVFPA readout circuit these methods were adopted, which including single-terminal amplifier under subthreshold region as CTIA amplifier, common current source load for source follow(SF) buffer in column pixels and level shift circuits, and time-sharing tail current source for column buffer. The smallest operational current of CTIA in pixel unit is only 8.5 nA with 3.3 V power supply by using single-terminal amplifier. The ROIC has been fabricated in SMIC 0.18 μm 1P6M mixed signal process and also achieved better performances with the novel design of bias current adjustable. Furthermore, the overall power consumption of the chip is 67.3 mW at 2 MHz in 8-outputs mode by the above methods according to the experimental results.
文摘A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution infrared focal plane array applications is proposed. The detector bias error in this structure is less than 0.1 mV. The input resistance is ideally zero, which is important to obtain high injection efficiency. Unit-cell occupies 10 μm × 15 μm area and consumes less than 0.4 mW power. Charge storag...
文摘The development of low-cost,non-enzymatic glucose biosensors is crucial for advancing accessible diabetes management.This paper presents the experimental testing of an extended-gate field-effect transistor(EG-FET)that uses a gold film as the sensing structure.The system innovatively employs a custom-designed inverting operational amplifier circuit for precise signal acquisition and an Arduino Nano platform for real-time data processing and visualization,eliminating the need for expensive laboratory equipment.At the core of the design is a depletion-mode MOSFET,whose current-voltage properties were characterized.The function of the sensor was demonstrated by testing its response to phosphate-buffered saline containing glucose at different concentrations.A clear modulation of the drain current in the linear region of the EG-FET was observed,and a preliminary analysis revealed a linear correlation between the output current and glucose concentration,indicating the system’s potential for quantitative detection.This study successfully validates the feasibility of a compact,cost-effective,and non-enzymatic EG-FET biosensing platform,establishing a solid foundation for future development of point-of-care diagnostic devices.
基金supported by the National Natural Science Foundation of China(No.61106025)the CAS/SAFEA International Partnership Program for Creative Research Teams
文摘Abstract： This paper presents a charge-sensitive-amplifier （CSA） based readout circuit for capacitive microelectro-mechanical-system （MEMS） sensors. A continuous-time （CT） readout structure using the chopper technique is adopted to cancel the low frequency noise and improve the resolution of the readout circuits. An operational trans-conductance amplifier （OTA） structure with an auxiliary common-mode-feedback-OTA is proposed in the fully differential CSA to suppress the chopper modulation induced disturbance at the OTA input terminal. An analog temperature compensation method is proposed, which adjusts the chopper signal amplitude with temperature variation to compensate the temperature drift of the CSA readout sensitivity. The chip is designed and implemented in a 0.35μm CMOS process and is 2.1 × 2.1 mm2 in area. The measurement shows that the readout circuit achieves 0.9 aF/√H capacitive resolution, 97 dB dynamic range in 100 Hz signal bandwidth, and 0.8 mV/fF sensitivity with a temperature drift of 35 ppm/℃ after optimized compensation.
基金supported by the National Natural Science Foundation of China (No.61006021)
文摘Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end circuit design.In this paper,we present a 0.18μm CMOS front-end readout circuit for low noise CdZnTe detectors in tens of pF capacitance.Solutions to the noise and gate leak problems in DSM technologies are discussed in detail.A prototype chip was designed,with a charge sensitive preamplifier,a 4th order semi-Gaussian shaper and several output drivers.Test results show that the chip has an equivalent noise charge of 164 e,without connecting it to a detector,with an integral nonlinearity of<0.21%and differential nonlinearity of<3.75%.
基金Supported by the National Natural Science Foundation of China (No.40704025)
文摘A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuous-time semi-Gaussian filter is chosen to avoid switch noise.The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application.The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology.Test results show the functions of the readout integrated circuit are correct.The equivalent noise charge with no detector connected is 500–700 e in the typical mode,the gain is tunable within 13–130 mV/fC and the peaking time varies from 0.7 to 1.6 μs,in which the average gain is about 20.5 mV/fC,and the linearity reaches 99.2%.
