An SF6/CF4 cyclic reactive-ion etching （RIE） method is proposed to suppress the surface roughness and to opti- mize the morphology of Ge fin, aiming at the fabrication of superior Ge FinFETs for future CMOS technolo...An SF6/CF4 cyclic reactive-ion etching （RIE） method is proposed to suppress the surface roughness and to opti- mize the morphology of Ge fin, aiming at the fabrication of superior Ge FinFETs for future CMOS technologies. The surface roughness of the Ge after RIE can be sufficiently reduced by introducing SF6-O2 etching steps into the CF4-O2 etching process, while maintaining a relatively large ratio of vertical etching over horizontal etching of the Ge. As a result, an optimized rms roughness of 0.9nm is achieved for Ge surfaces after the SF6/CF4 cyclic etching with a ratio of greater than four for vertical etching over horizontal etching of the Ge, by using a proportion of 60% for SF6-O2 etching steps.展开更多
This paper proposes to develop a data-driven via＇s depth estimator of the deep reactive ion etching process based on statistical identification of key variables.Several feature extraction algorithms are presented to ...This paper proposes to develop a data-driven via＇s depth estimator of the deep reactive ion etching process based on statistical identification of key variables.Several feature extraction algorithms are presented to reduce the high-dimensional data and effectively undertake the subsequent virtual metrology（VM） model building process.With the available on-line VM model,the model-based controller is hence readily applicable to improve the quality of a via＇s depth.Real operational data taken from a industrial manufacturing process are used to verify the effectiveness of the proposed method.The results demonstrate that the proposed method can decrease the MSE from 2.2×10^（-2） to 9×10^（-4） and has great potential in improving the existing DRIE process.展开更多
基金Supported by the National Basic Research Program of China under Grant No 2011CBA00607the National Natural Science Foundation of China under Grant No 61376097+1 种基金the Zhejiang Provincial Natural Science Foundation of China under Grant No LR14F040001Specialized Research Fund for the Doctoral Program of Higher Education of China under Grant No20130091110025
文摘An SF6/CF4 cyclic reactive-ion etching （RIE） method is proposed to suppress the surface roughness and to opti- mize the morphology of Ge fin, aiming at the fabrication of superior Ge FinFETs for future CMOS technologies. The surface roughness of the Ge after RIE can be sufficiently reduced by introducing SF6-O2 etching steps into the CF4-O2 etching process, while maintaining a relatively large ratio of vertical etching over horizontal etching of the Ge. As a result, an optimized rms roughness of 0.9nm is achieved for Ge surfaces after the SF6/CF4 cyclic etching with a ratio of greater than four for vertical etching over horizontal etching of the Ge, by using a proportion of 60% for SF6-O2 etching steps.
基金supported by the National Natural Science Foundation of China(No.60904053)the Natural Science Foundation of Jiangsu(No. SBK201123307)the Priority Academic Program Development of Jiangsu Higher Education Institutions(PAPD)
文摘This paper proposes to develop a data-driven via＇s depth estimator of the deep reactive ion etching process based on statistical identification of key variables.Several feature extraction algorithms are presented to reduce the high-dimensional data and effectively undertake the subsequent virtual metrology（VM） model building process.With the available on-line VM model,the model-based controller is hence readily applicable to improve the quality of a via＇s depth.Real operational data taken from a industrial manufacturing process are used to verify the effectiveness of the proposed method.The results demonstrate that the proposed method can decrease the MSE from 2.2×10^（-2） to 9×10^（-4） and has great potential in improving the existing DRIE process.
