According to increase of circuitry numbers of LSI, the test application time of a full scan design method becomes one of the bottleneck problems for the LSI productivity. The test application time is corresponding to ...According to increase of circuitry numbers of LSI, the test application time of a full scan design method becomes one of the bottleneck problems for the LSI productivity. The test application time is corresponding to the test length, thus the reduction of the test length in a scan design is strongly required. In this paper, we propose a partial scan design system at RT level design, named REPS, to reduce the test application time. REPS has the following new features: (1) a scan register selection method at RT level; (2) a DFT database is prepared to estimate test length of blocks; and (3) a DFT strategy generation for the shortest test length. We applied REPS to some test designs for a practical LSI that described at RT level. It is found that REPS estimates an accurate test length for an LSI at RTL, i.e. the error of the length is less than 10% from that at the gate level. As a result, the test length generated by the partial scan design method was 37% shorter than that by the conventional full scan design method.展开更多
文摘According to increase of circuitry numbers of LSI, the test application time of a full scan design method becomes one of the bottleneck problems for the LSI productivity. The test application time is corresponding to the test length, thus the reduction of the test length in a scan design is strongly required. In this paper, we propose a partial scan design system at RT level design, named REPS, to reduce the test application time. REPS has the following new features: (1) a scan register selection method at RT level; (2) a DFT database is prepared to estimate test length of blocks; and (3) a DFT strategy generation for the shortest test length. We applied REPS to some test designs for a practical LSI that described at RT level. It is found that REPS estimates an accurate test length for an LSI at RTL, i.e. the error of the length is less than 10% from that at the gate level. As a result, the test length generated by the partial scan design method was 37% shorter than that by the conventional full scan design method.
