设计了一种新的产生RSFQ时钟信号的电路,并利用W IN S软件对电路进行了模拟.它可以产生连续脉冲,脉冲的周期由电路中约瑟夫林传输线的长度决定,可以产生周期约10 ps的连续脉冲.经过扩展,这种电路能通过输入触发脉冲实现振荡的停止,从而...设计了一种新的产生RSFQ时钟信号的电路,并利用W IN S软件对电路进行了模拟.它可以产生连续脉冲,脉冲的周期由电路中约瑟夫林传输线的长度决定,可以产生周期约10 ps的连续脉冲.经过扩展,这种电路能通过输入触发脉冲实现振荡的停止,从而产生固定个数的时钟信号,产生时钟信号的数目由启动信号和停止信号的时间差决定;在电路中使用多路开关,还可以在不改变硬件电路的条件下,通过输入触发信号来改变输出时钟信号的周期.展开更多
The superconducting rapid single flux quantum(RSFQ)integrated circuit is a promising solu-tion for overcoming speed and power bottlenecks in high-performance computing systems in the post-Moore era.This paper presents...The superconducting rapid single flux quantum(RSFQ)integrated circuit is a promising solu-tion for overcoming speed and power bottlenecks in high-performance computing systems in the post-Moore era.This paper presents an architecture designed to improve the speed and power limitations of high-performance computing systems using superconducting technology.Since superconducting microprocessors,which operate at cryogenic temperatures,require support from semiconductor cir-cuits,the proposed design utilizes the von Neumann architecture with a superconducting RSFQ mi-croprocessor,cryogenic semiconductor memory,a room temperature field programmable gate array(FPGA)controller,and a host computer for input/output.Additionally,the paper introduces two key circuit designs:a start/stop controllable superconducting clock generator and an asynchronous communication interface between the RSFQ and semiconductor chips used to implement the control system.Experimental results demonstrate that the proposed design is feasible and effective,provi-ding valuable insights for future superconducting computer systems.展开更多
Rapid single flux quantum(RSFQ)circuits are a kind of superconducting digital circuits,having properties of a natural gate-level pipelining synchronous sequential circuit,which demonstrates high energy efficiency and ...Rapid single flux quantum(RSFQ)circuits are a kind of superconducting digital circuits,having properties of a natural gate-level pipelining synchronous sequential circuit,which demonstrates high energy efficiency and high throughput advantage.We find that the high-throughput and high-speed performance of RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm,whereas these are rarely applied to this field.Among the available encryption algorithms,the advanced encryption standard(AES)algorithm is an advanced encryption standard algorithm.It is currently the most widely used symmetric cryptography algorithm.In this work,we aim to demonstrate the SubByte operation of an AES-128 algorithm using RSFQ circuits based on the SIMIT Nb0_(3) process.We design an AES S-box circuit in the RSFQ logic,and compare its operational frequency,power dissipation,and throughput with those of the CMOS-based circuit post-simulated in the same structure.The complete RSFQ S-box circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz.Our analysis shows that the frequency and throughput of the RSFQ-based S-box are about four times higher than those of the CMOS-based S-box.Further,we design and fabricate a few typical modules of the S-box.Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz.展开更多
Two optimization technologies, namely, bypass and carry-control optimization, were demonstrated for enhancing the performance of a bit-slice Arithmetic Logic Unit (ALU) in 2n-bit Rapid Single-Flux-Quantum (RSFQ) micro...Two optimization technologies, namely, bypass and carry-control optimization, were demonstrated for enhancing the performance of a bit-slice Arithmetic Logic Unit (ALU) in 2n-bit Rapid Single-Flux-Quantum (RSFQ) microprocessors. These technologies can not only shorten the calculation time but also solve data hazards. Among them, the proposed bypass technology is applicable to any 2n-bit ALU, whether it is bit-serial, bit-slice or bit-parallel. The high performance bit-slice ALU was implemented using the 6 kA/cm^(2) Nb/AlOx/Nb junction fabrication process from Superconducting Electronics Facility of Shanghai Institute of Microsystem and Information Technology. It consists of 1693 Josephson junctions with an area of 2.46 0.81 mm^(2). All ALU operations of the MIPS32 instruction set are implemented, including two extended instructions, i.e., addition with carry (ADDC) and subtraction with borrow (SUBB). All the ALU operations were successfully obtained in SFQ testing based on OCTOPUX and the measured DC bias current margin can reach 86% - 104%. The ALU achieves a 100 utilization rate, regardless of carry/borrow read-after-write correlations between instructions.展开更多
Rapid‐Single‐Flux‐Quantum(RSFQ)circuit technology is well known for its low power consumption and latency,which enables digital signal processing up to tens of GHz.As a fundamental digital filter,the Finite Impulse...Rapid‐Single‐Flux‐Quantum(RSFQ)circuit technology is well known for its low power consumption and latency,which enables digital signal processing up to tens of GHz.As a fundamental digital filter,the Finite Impulse Response(FIR)filter has wide applications in communication systems.A design of an FIR filter based on RSFQ circuit technology is proposed.However,the FIR filter consumes large amounts of adders and multipliers.Based on Stochastic Computing(SC)theory with which adder and multiplier are much simpler,the hardware cost of FIR filter is dramatically reduced.A novel stochastic number generator(SNG),a stochastic‐tobinary converter(SBC),and the FIR filter were designed and verified via logic simulation with a target frequency of 10 GHz.The results indicated the FIR filter performs correct operations.The proposed FIR filter consists of 2255 Josephson junctions(JJs)without wiring cells(i.e.,Josephson Transmission Lines(JTLs),Passive Transmission Lines(PTLs)),which is acceptable,making it possible to be used in RSFQ digital signal processors.展开更多
文摘设计了一种新的产生RSFQ时钟信号的电路,并利用W IN S软件对电路进行了模拟.它可以产生连续脉冲,脉冲的周期由电路中约瑟夫林传输线的长度决定,可以产生周期约10 ps的连续脉冲.经过扩展,这种电路能通过输入触发脉冲实现振荡的停止,从而产生固定个数的时钟信号,产生时钟信号的数目由启动信号和停止信号的时间差决定;在电路中使用多路开关,还可以在不改变硬件电路的条件下,通过输入触发信号来改变输出时钟信号的周期.
基金the Strategic Priority Research Program of Chinese Academy of Sciences(No.XDA18000000)the National Natural Science Foundation of China(No.61732018,61872335).
文摘The superconducting rapid single flux quantum(RSFQ)integrated circuit is a promising solu-tion for overcoming speed and power bottlenecks in high-performance computing systems in the post-Moore era.This paper presents an architecture designed to improve the speed and power limitations of high-performance computing systems using superconducting technology.Since superconducting microprocessors,which operate at cryogenic temperatures,require support from semiconductor cir-cuits,the proposed design utilizes the von Neumann architecture with a superconducting RSFQ mi-croprocessor,cryogenic semiconductor memory,a room temperature field programmable gate array(FPGA)controller,and a host computer for input/output.Additionally,the paper introduces two key circuit designs:a start/stop controllable superconducting clock generator and an asynchronous communication interface between the RSFQ and semiconductor chips used to implement the control system.Experimental results demonstrate that the proposed design is feasible and effective,provi-ding valuable insights for future superconducting computer systems.
基金This work was supported by the National Natural Science Foundation of China(Grant No.92164101)the National Natural Science Foundation of China(Grant No.62171437)+2 种基金the Strategic Priority Research Program of the Chinese Academy of Sciences(Grant No.XDA18000000)Shanghai Science and Technology Committee(Grant No.21DZ1101000)the National Key R&D Program of China(Grant No.2021YFB0300400).
文摘Rapid single flux quantum(RSFQ)circuits are a kind of superconducting digital circuits,having properties of a natural gate-level pipelining synchronous sequential circuit,which demonstrates high energy efficiency and high throughput advantage.We find that the high-throughput and high-speed performance of RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm,whereas these are rarely applied to this field.Among the available encryption algorithms,the advanced encryption standard(AES)algorithm is an advanced encryption standard algorithm.It is currently the most widely used symmetric cryptography algorithm.In this work,we aim to demonstrate the SubByte operation of an AES-128 algorithm using RSFQ circuits based on the SIMIT Nb0_(3) process.We design an AES S-box circuit in the RSFQ logic,and compare its operational frequency,power dissipation,and throughput with those of the CMOS-based circuit post-simulated in the same structure.The complete RSFQ S-box circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz.Our analysis shows that the frequency and throughput of the RSFQ-based S-box are about four times higher than those of the CMOS-based S-box.Further,we design and fabricate a few typical modules of the S-box.Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz.
基金Strategic Priority Research Program of Chinese Academy of Sciences,under Grant XDA18000000.
文摘Two optimization technologies, namely, bypass and carry-control optimization, were demonstrated for enhancing the performance of a bit-slice Arithmetic Logic Unit (ALU) in 2n-bit Rapid Single-Flux-Quantum (RSFQ) microprocessors. These technologies can not only shorten the calculation time but also solve data hazards. Among them, the proposed bypass technology is applicable to any 2n-bit ALU, whether it is bit-serial, bit-slice or bit-parallel. The high performance bit-slice ALU was implemented using the 6 kA/cm^(2) Nb/AlOx/Nb junction fabrication process from Superconducting Electronics Facility of Shanghai Institute of Microsystem and Information Technology. It consists of 1693 Josephson junctions with an area of 2.46 0.81 mm^(2). All ALU operations of the MIPS32 instruction set are implemented, including two extended instructions, i.e., addition with carry (ADDC) and subtraction with borrow (SUBB). All the ALU operations were successfully obtained in SFQ testing based on OCTOPUX and the measured DC bias current margin can reach 86% - 104%. The ALU achieves a 100 utilization rate, regardless of carry/borrow read-after-write correlations between instructions.
基金supported in part by the Strategic Priority Research Program of Chinese Academy of Sciences,under Grant XDA18000000.
文摘Rapid‐Single‐Flux‐Quantum(RSFQ)circuit technology is well known for its low power consumption and latency,which enables digital signal processing up to tens of GHz.As a fundamental digital filter,the Finite Impulse Response(FIR)filter has wide applications in communication systems.A design of an FIR filter based on RSFQ circuit technology is proposed.However,the FIR filter consumes large amounts of adders and multipliers.Based on Stochastic Computing(SC)theory with which adder and multiplier are much simpler,the hardware cost of FIR filter is dramatically reduced.A novel stochastic number generator(SNG),a stochastic‐tobinary converter(SBC),and the FIR filter were designed and verified via logic simulation with a target frequency of 10 GHz.The results indicated the FIR filter performs correct operations.The proposed FIR filter consists of 2255 Josephson junctions(JJs)without wiring cells(i.e.,Josephson Transmission Lines(JTLs),Passive Transmission Lines(PTLs)),which is acceptable,making it possible to be used in RSFQ digital signal processors.
