RSA(Rivest-Shamir-Adleman)public-key cryptosystem is widely used in the information security area such as encryption and digital signature. Based on the modified Montgomery modular multiplication algorithm, a new arch...RSA(Rivest-Shamir-Adleman)public-key cryptosystem is widely used in the information security area such as encryption and digital signature. Based on the modified Montgomery modular multiplication algorithm, a new architecture using CSA(carry save adder)was presented to implement modular multiplication. Compared with the popular modular multiplication algorithms using two CSA, the presented algorithm uses only one CSA, so it can improve the time efficiency of RSA cryptoprocessor and save about half of hardware resources for modular multiplication. With the increase of encryption data size n, the clock cycles for the encryption procedure reduce in (T(n^2),) compared with the modular multiplication algorithms using two CSA.展开更多
RSA public key crypto system is a relatively safe technology, which is widely used in today’s secure electronic communication. In this paper, a new implementation method to optimize a 1 024 bit RSA processor was pres...RSA public key crypto system is a relatively safe technology, which is widely used in today’s secure electronic communication. In this paper, a new implementation method to optimize a 1 024 bit RSA processor was presented. Basically, a fast modular multiplication architecture based on Montgomery’s algorithm was proposed. Modular exponentiation algorithm scans encryption from right to left, so two modular multiplications can be processed parallel. The new architecture is also fit for an effective I/O interface. The time to calculate a modular exponentiation is about n 2 clock cycles. The proposed architecture has a data rate of 93.7 kb/s for 1 024 bit work with a 100 MHz clock.展开更多
Based on the analysis of several familiar large integer modular multiplication algorithms, this paper proposes a new Scalable Hybrid modular multiplication (SHyb) algorithm which has scalable operands, and presents an...Based on the analysis of several familiar large integer modular multiplication algorithms, this paper proposes a new Scalable Hybrid modular multiplication (SHyb) algorithm which has scalable operands, and presents an RSA algorithm model with scalable key size. Theoretical analysis shows that SHyb algorithm requires m 2 n /2 + 2miterations to complete an mn-bit modular multiplication with the application of an n-bit modular addition hardware circuit. The number of the required iterations can be reduced to a half of that of the scalable Montgomery algorithm. Consequently, the application scope of the RSA cryptosystem is expanded and its operation speed is enhanced based on SHyb al- gorithm.展开更多
In order to make the typical Montgomery’s algorithm suitable for implementation on FPGA, a modified version is proposed and then a high-performance systolic linear array architecture is designed for RSA cryptosystem ...In order to make the typical Montgomery’s algorithm suitable for implementation on FPGA, a modified version is proposed and then a high-performance systolic linear array architecture is designed for RSA cryptosystem on the basis of the optimized algorithm. The proposed systolic array architecture has dis- tinctive features, i.e. not only the computation speed is significantly fast but also the hardware overhead is drastically decreased. As a major practical result, the paper shows that it is possible to implement public-key cryptosystem at secure bit lengths on a single commercially available FPGA.展开更多
文摘RSA(Rivest-Shamir-Adleman)public-key cryptosystem is widely used in the information security area such as encryption and digital signature. Based on the modified Montgomery modular multiplication algorithm, a new architecture using CSA(carry save adder)was presented to implement modular multiplication. Compared with the popular modular multiplication algorithms using two CSA, the presented algorithm uses only one CSA, so it can improve the time efficiency of RSA cryptoprocessor and save about half of hardware resources for modular multiplication. With the increase of encryption data size n, the clock cycles for the encryption procedure reduce in (T(n^2),) compared with the modular multiplication algorithms using two CSA.
基金NSF of U nited States under Contract 5 978East Asia and Pacific Program(960 2 485 )
文摘RSA public key crypto system is a relatively safe technology, which is widely used in today’s secure electronic communication. In this paper, a new implementation method to optimize a 1 024 bit RSA processor was presented. Basically, a fast modular multiplication architecture based on Montgomery’s algorithm was proposed. Modular exponentiation algorithm scans encryption from right to left, so two modular multiplications can be processed parallel. The new architecture is also fit for an effective I/O interface. The time to calculate a modular exponentiation is about n 2 clock cycles. The proposed architecture has a data rate of 93.7 kb/s for 1 024 bit work with a 100 MHz clock.
文摘Based on the analysis of several familiar large integer modular multiplication algorithms, this paper proposes a new Scalable Hybrid modular multiplication (SHyb) algorithm which has scalable operands, and presents an RSA algorithm model with scalable key size. Theoretical analysis shows that SHyb algorithm requires m 2 n /2 + 2miterations to complete an mn-bit modular multiplication with the application of an n-bit modular addition hardware circuit. The number of the required iterations can be reduced to a half of that of the scalable Montgomery algorithm. Consequently, the application scope of the RSA cryptosystem is expanded and its operation speed is enhanced based on SHyb al- gorithm.
文摘In order to make the typical Montgomery’s algorithm suitable for implementation on FPGA, a modified version is proposed and then a high-performance systolic linear array architecture is designed for RSA cryptosystem on the basis of the optimized algorithm. The proposed systolic array architecture has dis- tinctive features, i.e. not only the computation speed is significantly fast but also the hardware overhead is drastically decreased. As a major practical result, the paper shows that it is possible to implement public-key cryptosystem at secure bit lengths on a single commercially available FPGA.
