In this paper,a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter(SAR ADC)is developed by the CMOS 0.25μm process.An on-chip all-digital foreground weights calibration ...In this paper,a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter(SAR ADC)is developed by the CMOS 0.25μm process.An on-chip all-digital foreground weights calibration technique integrating self-calibration weight measurement with PN port auto-balance technique is designed to improve the performance and lower the costs of the developed SAR ADC.The SAR ADC has a chip area of 2.7×2.4 mm^2,and consumes only 100μW at the 2.5 V supply voltage with 100 KSPS.The INL and DNL are both less than 0.5 LSB.展开更多
文摘In this paper,a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter(SAR ADC)is developed by the CMOS 0.25μm process.An on-chip all-digital foreground weights calibration technique integrating self-calibration weight measurement with PN port auto-balance technique is designed to improve the performance and lower the costs of the developed SAR ADC.The SAR ADC has a chip area of 2.7×2.4 mm^2,and consumes only 100μW at the 2.5 V supply voltage with 100 KSPS.The INL and DNL are both less than 0.5 LSB.
