Technology development and continuous down scaling in CMOS fabrication makes Mixed Signal Integrated Circuits (MSIC) more vulnerable to process variation. This paper presents a well defined novel design methodology fo...Technology development and continuous down scaling in CMOS fabrication makes Mixed Signal Integrated Circuits (MSIC) more vulnerable to process variation. This paper presents a well defined novel design methodology for process variability aware design by incorporating the major challenge of statistical circuit performance relating the device and circuit level variation in an accurate and efficient manner to improve the reliability, robustness and stability of the circuit. The device sensitive parameters are identified and accurately quantified by continuous realistic assessments using statistical methods. The modularity of the methodology can be validated by the output performance obtained from the gain and phase response of OTA which is highly stable when subjected to worst case process variation scenario. In the proposed optimization, the circuit is strengthened by fixing the optimum aspect ratio without adding any additional compensation devices complicating the circuit resulting in low power consumption of only 0.116 mW in standard CMOS 0.18 μm technology with 1.8 V power supply.展开更多
A lowtemperature coefficient（ TC） bandgap reference（ BGR） with novel process variation calibration technique is proposed in this paper. This proposed calibration technique compensating both TC and output value of ...A lowtemperature coefficient（ TC） bandgap reference（ BGR） with novel process variation calibration technique is proposed in this paper. This proposed calibration technique compensating both TC and output value of BGR achieves fine adjustment step towards the reference voltage,while keeping optimal TC by utilizing large resistance to help layout match. The high-order curvature compensation realized by poly and p-diffusion resistors is introduced into the design to guarantee the temperature characteristic. Implemented in 180 nm technology,the proposed BGR has been simulated to have a power supply rejection ratio（ PSRR） of 91 dB@100 Hz. The calibration technique covers output voltage scope of 0. 49 V-0. 56 Vwith TC of 9. 45 × 10^（-6）/℃-9. 56 × 10^（-6）/℃ over the temperature range of-40 ℃-120 ℃. The designed BGR provides a reference voltage of 500 mV,with measured TC of 10. 1 × 10^（-6）/℃.展开更多
This paper presents the design and measured performance ofa wideband amplifier for a direct conversion satellite tuner. It is composed of a wideband low noise amplifier （LNA） and a two-stage RF variable gain amplifi...This paper presents the design and measured performance ofa wideband amplifier for a direct conversion satellite tuner. It is composed of a wideband low noise amplifier （LNA） and a two-stage RF variable gain amplifier （VGA） with linear gain in dB and temperature compensation schemes. To meet the system linearity requirement, an improved distortion compensation technique and a bypass mode are applied on the LNA to deal with the large input signal. Wideband matching is achieved by resistive feedback and an off-chip LC-ladder matching network. A large gain control range （over 80 dB） is achieved by the VGA with process voltage and temperature compensation and dB linearization. In total, the amplifier consumes up to 26 mA current from a 3.3 V power supply. It is fabricated in a 0.35μm SiGe BiCMOS technology and occupies a silicon area of 0.25 mm^2.展开更多
文摘Technology development and continuous down scaling in CMOS fabrication makes Mixed Signal Integrated Circuits (MSIC) more vulnerable to process variation. This paper presents a well defined novel design methodology for process variability aware design by incorporating the major challenge of statistical circuit performance relating the device and circuit level variation in an accurate and efficient manner to improve the reliability, robustness and stability of the circuit. The device sensitive parameters are identified and accurately quantified by continuous realistic assessments using statistical methods. The modularity of the methodology can be validated by the output performance obtained from the gain and phase response of OTA which is highly stable when subjected to worst case process variation scenario. In the proposed optimization, the circuit is strengthened by fixing the optimum aspect ratio without adding any additional compensation devices complicating the circuit resulting in low power consumption of only 0.116 mW in standard CMOS 0.18 μm technology with 1.8 V power supply.
基金Supported by the National Natural Science Foundation of China(61604109)the National High-Tech R&D Program of China(2015AA042605)
文摘A lowtemperature coefficient（ TC） bandgap reference（ BGR） with novel process variation calibration technique is proposed in this paper. This proposed calibration technique compensating both TC and output value of BGR achieves fine adjustment step towards the reference voltage,while keeping optimal TC by utilizing large resistance to help layout match. The high-order curvature compensation realized by poly and p-diffusion resistors is introduced into the design to guarantee the temperature characteristic. Implemented in 180 nm technology,the proposed BGR has been simulated to have a power supply rejection ratio（ PSRR） of 91 dB@100 Hz. The calibration technique covers output voltage scope of 0. 49 V-0. 56 Vwith TC of 9. 45 × 10^（-6）/℃-9. 56 × 10^（-6）/℃ over the temperature range of-40 ℃-120 ℃. The designed BGR provides a reference voltage of 500 mV,with measured TC of 10. 1 × 10^（-6）/℃.
文摘This paper presents the design and measured performance ofa wideband amplifier for a direct conversion satellite tuner. It is composed of a wideband low noise amplifier （LNA） and a two-stage RF variable gain amplifier （VGA） with linear gain in dB and temperature compensation schemes. To meet the system linearity requirement, an improved distortion compensation technique and a bypass mode are applied on the LNA to deal with the large input signal. Wideband matching is achieved by resistive feedback and an off-chip LC-ladder matching network. A large gain control range （over 80 dB） is achieved by the VGA with process voltage and temperature compensation and dB linearization. In total, the amplifier consumes up to 26 mA current from a 3.3 V power supply. It is fabricated in a 0.35μm SiGe BiCMOS technology and occupies a silicon area of 0.25 mm^2.
