The precise compact modeling of magnetic devices is pivotal for the integrated design of spin-transfer torque magnetic tunnel junction(STT-MTJ)in conjunction with CMOS circuitry.This work presents a macro model for an...The precise compact modeling of magnetic devices is pivotal for the integrated design of spin-transfer torque magnetic tunnel junction(STT-MTJ)in conjunction with CMOS circuitry.This work presents a macro model for an STT-MTJ which is compatible with SPICE simulation platforms.The model accurately replicates the electrical performance of the MTJ,encompassing the resistance-voltage characteristics and the pulse-width-dependent state switching behavior,and is validated with various experimental data.Additionally,the impact of process variations,particularly those affecting the MTJ diameter and barrier thickness is investigated and summarized in a corner model.Monte Carlo simulations demonstrate that our adaptable and streamlined model can be efficiently incorporated into the design of integrated circuits.展开更多
With technology scaling,stability,power dissipation,and device variability,the impact of process,voltage and temperature(PVT)variations has become dominant for static random access memory(SRAM)analysis for productivit...With technology scaling,stability,power dissipation,and device variability,the impact of process,voltage and temperature(PVT)variations has become dominant for static random access memory(SRAM)analysis for productivity and failure.In this paper,ten-transistors(10T)and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors(FGMOS).Power centric parameters viz.read power,write power,hold power and delay are the performance analysis metrics.Further,the stochastic parameter variation to study the variability tolerance of the redesigned cell,PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell.Stability has been illustrated with the conventional butterfly method giving read static noise margin(RSNM)and write static noise margin(WSNM)metrics for read stability and write ability,respectively.A comparative analysis with standard six-transistor SRAM cell is carried out.HSPICE simulative analysis has been carried out for 32 nm technology node.The redesigned FGMOS SRAM cells provide improved performance.Also,these are robust and reliability efficient with comparable stability.展开更多
基金Project supported by the National Science and Technology Major Project of China(Grant No.2020AAA0109003)。
文摘The precise compact modeling of magnetic devices is pivotal for the integrated design of spin-transfer torque magnetic tunnel junction(STT-MTJ)in conjunction with CMOS circuitry.This work presents a macro model for an STT-MTJ which is compatible with SPICE simulation platforms.The model accurately replicates the electrical performance of the MTJ,encompassing the resistance-voltage characteristics and the pulse-width-dependent state switching behavior,and is validated with various experimental data.Additionally,the impact of process variations,particularly those affecting the MTJ diameter and barrier thickness is investigated and summarized in a corner model.Monte Carlo simulations demonstrate that our adaptable and streamlined model can be efficiently incorporated into the design of integrated circuits.
文摘With technology scaling,stability,power dissipation,and device variability,the impact of process,voltage and temperature(PVT)variations has become dominant for static random access memory(SRAM)analysis for productivity and failure.In this paper,ten-transistors(10T)and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors(FGMOS).Power centric parameters viz.read power,write power,hold power and delay are the performance analysis metrics.Further,the stochastic parameter variation to study the variability tolerance of the redesigned cell,PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell.Stability has been illustrated with the conventional butterfly method giving read static noise margin(RSNM)and write static noise margin(WSNM)metrics for read stability and write ability,respectively.A comparative analysis with standard six-transistor SRAM cell is carried out.HSPICE simulative analysis has been carried out for 32 nm technology node.The redesigned FGMOS SRAM cells provide improved performance.Also,these are robust and reliability efficient with comparable stability.
