Due to interaction among cells, it is too complex to build an exactanalytical model for the power dissipation within the cell membrane in suspensions exposed toexternal fields. An approximate equivalence method is pro...Due to interaction among cells, it is too complex to build an exactanalytical model for the power dissipation within the cell membrane in suspensions exposed toexternal fields. An approximate equivalence method is proposed to resolve this problem. Based on theeffective medium theory, the transmembrane voltage on cells in suspensions was investigated by theequivalence principle. Then the electric field in the cell membrane was determined. Finally,analytical solutions for the power dissipation within the cell membrane in suspensions exposed toexternal fields were derived according to the Joule principle. The equations show that theconductive power dissipation is predominant within the cell membrane in suspensions exposed todirect current or lower frequencies, and dielectric power dissipation prevails at high frequenciesexceeding the relaxation frequency of the exposed membrane.展开更多
The power dissipation characteristics of pulsed power switch reversely switched dynistors （RSDs） are investigated in this paper. According to the expressions of voltage on RSD, derived from the plasma bipolar drift ...The power dissipation characteristics of pulsed power switch reversely switched dynistors （RSDs） are investigated in this paper. According to the expressions of voltage on RSD, derived from the plasma bipolar drift model and the RLC circuit equations of RSD main loop, the simulation waveforms of current and voltage on RSD are acquired through iterative calculation by using the fourth order Runge-Kutta method, then the curve of transient power on RSD versus time is obtained. The result shows that the total dissipation on RSD is trivial compared with the pulse discharge energy and the commutation dissipation can be nearly ignored compared with the quasi-static dissipation. These characteristics can make the repetitive frequency of RSD increase largely. The experimental results prove the validity of simulation calculations. The influence factors on power dissipation are discussed. The power dissipation increases with the increase of the peak current and the n-base width and with the decrease of n-base doping concentration. In order to keep a low power dissipation, it is suggested that the n-base width should be smaller than 320μm when doping concentration is 1.0×10^14cm^-3 while the doping concentration should be higher than 5.8×10^13cm^-3 when n-base width is 270μm.展开更多
We presented 980-nm oxide-confined vertical-cavity surface-emitting lasers （VCSELs） with a 16 -um oxide aperture. Optical power, voltage, and emission wavelength are measured in an ambient temperature range of 5 ℃-...We presented 980-nm oxide-confined vertical-cavity surface-emitting lasers （VCSELs） with a 16 -um oxide aperture. Optical power, voltage, and emission wavelength are measured in an ambient temperature range of 5 ℃-80 ℃. Measurements combined with an empirical model are used to analyse the power dissipation in the device and the physical mechanism contributing to the thermal rollover phenomenon in VCSEL. It is found that the carrier leakage induced selfheating in the active region and the Joule heating caused by the series resistance are the main sources of power dissipation. In addition, carrier leakage induced self-heating increases as the injection current increases, resulting in a rapid decrease of the internal quantum efficiency, which is a dominant contribution to the thermal rollover of the VCSEL at a larger current. Our study provides useful guidelines to design a 980-nm oxide-confined VCSEL for thermal performance enhancement.展开更多
A method of non-uniform finger spacing is proposed to enhance thermal stability of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations. Temperature distribution on the emi...A method of non-uniform finger spacing is proposed to enhance thermal stability of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations. Temperature distribution on the emitter fingers of a multi-finger SiGe heterojunction bipolar transistor is studied using a numerical electro-thermal model. The results show that the SiGe heterojunction bipolar transistor with non-uniform finger spacing has a small temperature difference between fingers compared with a traditional uniform finger spacing heterojunction bipolar transistor at the same power dissipation. What is most important is that the ability to improve temperature non-uniformity is not weakened as power dissipation increases. So the method of non-uniform finger spacing is very effective in enhancing the thermal stability and the power handing capability of power device. Experimental results verify our conclusions.展开更多
The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The t...The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.展开更多
During ion cyclotron resonance heating,the sheath power dissipation caused by ion acceleration in the radio frequency(RF)sheath is one of the main causes of RF power loss in the tokamak edge region.To estimate the pow...During ion cyclotron resonance heating,the sheath power dissipation caused by ion acceleration in the radio frequency(RF)sheath is one of the main causes of RF power loss in the tokamak edge region.To estimate the power dissipation of an RF sheath in the ion cyclotron range of frequency(ICRF),a 1 D fluid model for the multi-component plasma sheath driven by a sinusoidal disturbance current in the ICRF is presented.By investigation of the sheath potential and ion flux at the wall,it is shown that the larger frequency and lower amplitude of the disturbance current can cause smaller sheath power dissipation.The effect of the energetic ion on the sheath power dissipation depends on the disturbance current.For large amplitude of disturbance current,the increase in the concentration and energy of the energetic ion leads to a decrease in sheath power dissipation.While for a small disturbance current,the sheath power dissipation demonstrates non-monotonic variation with the concentration and energy of the energetic ion.In addition,the sheath power dissipation is found to have a small increase in the presence of light impurity ions with low valence.展开更多
In this paper, the glitching activity and process variations in the maximum power dissipation estimation of CMOS circuits are introduced. Given a circuit and the gate library, a new Genetic Algorithm (GA)-based techni...In this paper, the glitching activity and process variations in the maximum power dissipation estimation of CMOS circuits are introduced. Given a circuit and the gate library, a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view. The simulation on 1SCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02. Compared with the traditional Monte Carlo-based technique, the new approach presented in this paper is more effective.展开更多
In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware m...In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.展开更多
Using state assignment to minimize power dissipation and area for finite state ma-chines is computationally hard. Most of published results show that the reduction of switchingactivity often trades with area penalty. ...Using state assignment to minimize power dissipation and area for finite state ma-chines is computationally hard. Most of published results show that the reduction of switchingactivity often trades with area penalty. In this paper, a new approach is proposed. Experimentalresults show a significant reduction of switching activity without area penalty compared withprevious publications.展开更多
The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator ...The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm （MCNA） is first introduced, and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio （Rp）. For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.展开更多
This paper presents a partition-based Design-for- Test （DFT） technique to reduce the power consumption during scan-based testing. This method is based on partitioning the chip into several independent scan domains. ...This paper presents a partition-based Design-for- Test （DFT） technique to reduce the power consumption during scan-based testing. This method is based on partitioning the chip into several independent scan domains. By enabling the scan domains alternatively, only a fraction of the entire chip will be active at the same time, leading to low power consumption during test. Therefore, it will significantly reduce the possibility of Electronic Migration and Overheating. In order to prevent the drop of fault coverage, wrappers on the boundaries between scan domains are employed. This paper also presents a detailed design flow based on Electronics Design Automation （EDA） tools from Synopsy~ to implement the proposed test structure. The proposed DFT method is experimented on a state-of-theart System-ou-chips （SOC）. The simulation results show a significant reduction in both average and peak power dissipation without sacrificing the fault coverage and test time. This SOC has been taped out in TSMC and finished the final test m ADVANTEST.展开更多
Power dissipation has become one of the key optimization conditions in logic design on field programmable gate arrays （FPGAs）, thus the power estimation is necessary for logic design optimization. Nowadays, signal a...Power dissipation has become one of the key optimization conditions in logic design on field programmable gate arrays （FPGAs）, thus the power estimation is necessary for logic design optimization. Nowadays, signal activity data created by logic simulation based on test vectors is essential to be used to determine the toggle rate of each signals and blocks in power estimation tools provided by field programmable gate array （FPGA） electronic design automation （EDA） tools. The accuracy of power estimation highly depends on the quality of test vectors, especially, pattern coverage. As probability distribution can describe the uncertainty signals, this work provides an algorithm which can estimate FPGAs power more effectively and accurately by using signal probability distribution rather than test vectors.展开更多
Flow behaviors of spray forming low solvus high refractory (LSHR) alloy were investigated using hot compression tests performed on a Gleeble?3500 thermal mechanical simulator at temperatures of 1020?1150 °C and s...Flow behaviors of spray forming low solvus high refractory (LSHR) alloy were investigated using hot compression tests performed on a Gleeble?3500 thermal mechanical simulator at temperatures of 1020?1150 °C and strain rates of 0.0003?1.0 s?1. The constitutive equation was established, power dissipation (η) maps and hot processing maps were plotted. The microstructure evolution and dislocation distribution of domains with different values of η in power dissipation maps were also observed. The results show that the flow stress increases with decreasing temperature and increasing strain rate. The activation energy of the spray forming LSHR alloy is 1243.86 kJ/mol. When the value of η is 0.36 at the strain of 0.5, the domain in the processing map shows characteristics of typical dynamic recrystallization (DRX) and low dislocation density. According to the microstructure evolution and processing maps, the optimum processing condition for good hot workability of spray forming LSHR alloy can be summed up as:temperature range 1110?1150 °C; strain rate range 0.01?0.3 s?1.展开更多
The mechanical behavior of 2124 Al alloy produced by powder metallurgy was investigated with compression test at different temperatures and strain rates. The tests were performed in the temperature range of 300℃～500...The mechanical behavior of 2124 Al alloy produced by powder metallurgy was investigated with compression test at different temperatures and strain rates. The tests were performed in the temperature range of 300℃～500℃ and at strain rates from 0.001 s^-1 to 1.0 s^-1. The compression flow curves exhibited an initial sharp increase with strain, followed by monotonous hardening. The maximum stress decreased with decreasing strain rate and increasing temperature. The hot deformation characteristics of the material were studied using processing maps. The domain of safety and unsafe regime were identified and validated through microstructural examination.展开更多
Isothermal compression tests of as-forged 30Si2MnCrMoVE low-alloying ultra-high-strength steel were carried out on a Gleeble 3500 thermal simulator at the deformation temperatures of 950-1150℃and strain rates of 0.01...Isothermal compression tests of as-forged 30Si2MnCrMoVE low-alloying ultra-high-strength steel were carried out on a Gleeble 3500 thermal simulator at the deformation temperatures of 950-1150℃and strain rates of 0.01-10 s^−1.Based on the classical stress-dislocation density relationship and the kinematics of the dynamic recrystallization,the constitutive equations of the work hardening dynamical recovery period and dynamical recrystallization period were developed by using the work hardening curve and Avrami equation,which shows good agreement with the experimental value.Processing maps at the strain of 0.90 were constructed based on dynamic material model and were analyzed combined with microstructure observation under different conditions.The optimum parameter based on the processing maps was obtained and verified by a supplementary experiment.The power dissipation maps and instability maps at strains of 0.05-0.90 were also constructed,and the evolution law was analyzed in detail.The established constitutive equation and hot processing maps can provide some guidance for hot working process.展开更多
The hot deformation behavior of IN706 has been investigated by means of hot compression tests in the temperature range of 900-1150℃ and strain rate range of 0.001-1 s^-1. The constitutive equation was developed on th...The hot deformation behavior of IN706 has been investigated by means of hot compression tests in the temperature range of 900-1150℃ and strain rate range of 0.001-1 s^-1. The constitutive equation was developed on the basis of experimental data. Power dissipation efficiency （η） and instability parameter （4） maps were evaluated using the principles of the dynamic material model. Furthermore, the EBSD microstructure analysis was performed for validation, revealing that η was closely associated with the mechanism of dynamic recrystallization （DRX）. Microstructure transition map was composed of contour plots of η, 4, and DRX. The DRX domain zones and instable zones were identified in the processing map and were classified based on η. In a view of microstructure refinement and workability improvement, the optimum processing should be selected in the temperature range of 970-1025 ~C and the strain rate range of 0.08-0.01 s^-1.展开更多
In this paper,we consider solving the topology optimization for steady-state incompressibleNavier-Stokes problems via a new topology optimization method called parameterized level set method,which can maintain a relat...In this paper,we consider solving the topology optimization for steady-state incompressibleNavier-Stokes problems via a new topology optimization method called parameterized level set method,which can maintain a relatively smooth level set function with a local optimality condition.The objective of topology optimization is tond an optimal conguration of theuid and solid materials that minimizes power dissipation under a prescribeduid volume fraction constraint.An articial friction force is added to the Navier-Stokes equations to apply the no-slip boundary condition.Although a great deal of work has been carried out for topology optimization ofuidow in recent years,there are few researches on the topology optimization ofuidow with physical body forces.To simulate theuidow in reality,the constant body force(e.g.,gravity)is considered in this paper.Several 2D numerical examples are presented to discuss the relationships between the proposed method with Reynolds number and initial design,and demonstrate the feasibility and superiority of the proposed method in dealing with unstructuredmesh problems.Three 3D numerical examples demonstrate the proposedmethod is feasible in three-dimensional.展开更多
Repeater optimization is the key for SOC （System on Chip） interconnect delay design. This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance...Repeater optimization is the key for SOC （System on Chip） interconnect delay design. This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines. It also presents Lagrangian function to find the number of repeaters and their sizes required for minimizing area and power overhead with target delay constraint. Based on the 65 nanometre CMOS technology, the computed results of the intermediate and global lines show that the proposed model can significantly reduce area and power of interconnected lines, and the better performance will be achieved with the longer line. The results compared with the reference paper demonstrate the validity of this model. It can be integrated into repeater design methodology and CAD （computer aided design） tool for interconnect planning in nanometre SOC.展开更多
The true stress–true strain curves of 25Cr2Ni4MoVA steel were obtained by uniaxial compression experiments at 850–1200℃ in the strain rate range of 0.001–10.0 s^(−1).And the dynamic continuous cooling transformati...The true stress–true strain curves of 25Cr2Ni4MoVA steel were obtained by uniaxial compression experiments at 850–1200℃ in the strain rate range of 0.001–10.0 s^(−1).And the dynamic continuous cooling transformation curves were obtained at the cooling rate range of 0.5–15.0℃ s^(−1) from the austenitization temperature of 1000℃ to the room temperature by pre-strain of 0.2 as well.The power dissipation map and the dynamic continuous cooling transformation diagram were constructed based on the data provided by these curves.Compared with the optical micrographs of the compressed samples,the full dynamic recrystallization region is located between 1000 and 1200℃ and at the strain rate range from 0.01 to 10.0 s^(−1) with the power dissipation efficiency not less than 0.33.In the full dynamic recrystallization region,the power dissipation efficiency increases and the dynamic recrystallization activation energy decreases with the temperature increasing.With the strain rate decreasing,the power dissipation efficiency increases firstly and then starts to decrease as the strain rate is less than 0.1 s^(−1),and dynamic recrystallization activation energy changes on the contrary.According to the dynamic continuous cooling transformation diagram,slow cooling is a better way for the hot-deformed piece with large size or complex shape to avoid cracking as the temperature of the piece is lower than 400℃,and different cooling ways can be used for the hot-deformed piece with small size and simple shapes to obtain certain microstructure and meet good compressive properties.展开更多
The classification of tropical cyclones(TCs) is significant to obtaining their temporal and spatial variation characteristics in the context of dramatic-changing global climate. A new TCs clustering method by using K-...The classification of tropical cyclones(TCs) is significant to obtaining their temporal and spatial variation characteristics in the context of dramatic-changing global climate. A new TCs clustering method by using K-means clustering algorithm with nine physical indexes is proposed in the paper. Each TC is quantified into an 11-dimensional vector concerning trajectory attributes, time attributes and power attributes. Two recurving clusters(cluster A and E)and three straight-moving clusters(cluster B, C and D) are categorized from the TC best-track dataset of the western North Pacific(WNP) over the period of 1949-2013, and TCs' properties have been analyzed and compared in different aspects. The calculation results of coefficient variation(CV) and Nash-Sutcliffe efficiency(NSE) reveal a high level of intra-cluster cohesiveness and inter-cluster divergence, which means that the physical index system could serve as a feasible method of TCs classification. The clusters are then analyzed in terms of trajectory, lifespan, seasonality, trend,intensity and Power Dissipation Index(PDI). The five classified clusters show distinct features in TCs' temporal and spatial development discipline. Moreover, each cluster has its individual motion pattern, variation trend, influence region and impact degree.展开更多
文摘Due to interaction among cells, it is too complex to build an exactanalytical model for the power dissipation within the cell membrane in suspensions exposed toexternal fields. An approximate equivalence method is proposed to resolve this problem. Based on theeffective medium theory, the transmembrane voltage on cells in suspensions was investigated by theequivalence principle. Then the electric field in the cell membrane was determined. Finally,analytical solutions for the power dissipation within the cell membrane in suspensions exposed toexternal fields were derived according to the Joule principle. The equations show that theconductive power dissipation is predominant within the cell membrane in suspensions exposed todirect current or lower frequencies, and dielectric power dissipation prevails at high frequenciesexceeding the relaxation frequency of the exposed membrane.
基金supported by the National Natural Science Foundation of China (Grant Nos 50277016 and 50577028)supported by the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No 20050487044)
文摘The power dissipation characteristics of pulsed power switch reversely switched dynistors （RSDs） are investigated in this paper. According to the expressions of voltage on RSD, derived from the plasma bipolar drift model and the RLC circuit equations of RSD main loop, the simulation waveforms of current and voltage on RSD are acquired through iterative calculation by using the fourth order Runge-Kutta method, then the curve of transient power on RSD versus time is obtained. The result shows that the total dissipation on RSD is trivial compared with the pulse discharge energy and the commutation dissipation can be nearly ignored compared with the quasi-static dissipation. These characteristics can make the repetitive frequency of RSD increase largely. The experimental results prove the validity of simulation calculations. The influence factors on power dissipation are discussed. The power dissipation increases with the increase of the peak current and the n-base width and with the decrease of n-base doping concentration. In order to keep a low power dissipation, it is suggested that the n-base width should be smaller than 320μm when doping concentration is 1.0×10^14cm^-3 while the doping concentration should be higher than 5.8×10^13cm^-3 when n-base width is 270μm.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60908012 and 61076148)the Foundation of Beijing Municipal Education Commission, China (Grant No. KM201010005030)
文摘We presented 980-nm oxide-confined vertical-cavity surface-emitting lasers （VCSELs） with a 16 -um oxide aperture. Optical power, voltage, and emission wavelength are measured in an ambient temperature range of 5 ℃-80 ℃. Measurements combined with an empirical model are used to analyse the power dissipation in the device and the physical mechanism contributing to the thermal rollover phenomenon in VCSEL. It is found that the carrier leakage induced selfheating in the active region and the Joule heating caused by the series resistance are the main sources of power dissipation. In addition, carrier leakage induced self-heating increases as the injection current increases, resulting in a rapid decrease of the internal quantum efficiency, which is a dominant contribution to the thermal rollover of the VCSEL at a larger current. Our study provides useful guidelines to design a 980-nm oxide-confined VCSEL for thermal performance enhancement.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60776051,61006059and61006044)the Beijing Municipal Natural Science Foundation,China(Grant No.4082007)the Beijing Municipal Education Committee,China(Grant Nos.KM200710005015and KM200910005001)
文摘A method of non-uniform finger spacing is proposed to enhance thermal stability of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations. Temperature distribution on the emitter fingers of a multi-finger SiGe heterojunction bipolar transistor is studied using a numerical electro-thermal model. The results show that the SiGe heterojunction bipolar transistor with non-uniform finger spacing has a small temperature difference between fingers compared with a traditional uniform finger spacing heterojunction bipolar transistor at the same power dissipation. What is most important is that the ability to improve temperature non-uniformity is not weakened as power dissipation increases. So the method of non-uniform finger spacing is very effective in enhancing the thermal stability and the power handing capability of power device. Experimental results verify our conclusions.
基金Supported by the Guangdong Provincial Natural Science Foundation of China(2014A030313441)the Guangzhou Science and Technology Project(201510010169)+1 种基金the Guangdong Province Science and Technology Project(2016B090918071,2014A040401076)the National Natural Science Foundation of China(61072028)
文摘The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.
基金supported by National Natural Science Foundation of China(Grant No.11775257)。
文摘During ion cyclotron resonance heating,the sheath power dissipation caused by ion acceleration in the radio frequency(RF)sheath is one of the main causes of RF power loss in the tokamak edge region.To estimate the power dissipation of an RF sheath in the ion cyclotron range of frequency(ICRF),a 1 D fluid model for the multi-component plasma sheath driven by a sinusoidal disturbance current in the ICRF is presented.By investigation of the sheath potential and ion flux at the wall,it is shown that the larger frequency and lower amplitude of the disturbance current can cause smaller sheath power dissipation.The effect of the energetic ion on the sheath power dissipation depends on the disturbance current.For large amplitude of disturbance current,the increase in the concentration and energy of the energetic ion leads to a decrease in sheath power dissipation.While for a small disturbance current,the sheath power dissipation demonstrates non-monotonic variation with the concentration and energy of the energetic ion.In addition,the sheath power dissipation is found to have a small increase in the presence of light impurity ions with low valence.
基金Supported by NSF of the United States under contract 5978 East Asia and Pacific Program 9602485
文摘In this paper, the glitching activity and process variations in the maximum power dissipation estimation of CMOS circuits are introduced. Given a circuit and the gate library, a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view. The simulation on 1SCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02. Compared with the traditional Monte Carlo-based technique, the new approach presented in this paper is more effective.
基金supported partially by the National High Technical Research and Development Program of China (863 Program) under Grants No. 2011AA040101, No. 2008AA01Z134the National Natural Science Foundation of China under Grants No. 61003251, No. 61172049, No. 61173150+2 种基金the Doctoral Fund of Ministry of Education of China under Grant No. 20100006110015Beijing Municipal Natural Science Foundation under Grant No. Z111100054011078the 2012 Ladder Plan Project of Beijing Key Laboratory of Knowledge Engineering for Materials Science under Grant No. Z121101002812005
文摘In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.
基金Supported by NNSF of China(Key International Cooperative Project No.60010121219)
文摘Using state assignment to minimize power dissipation and area for finite state ma-chines is computationally hard. Most of published results show that the reduction of switchingactivity often trades with area penalty. In this paper, a new approach is proposed. Experimentalresults show a significant reduction of switching activity without area penalty compared withprevious publications.
基金Supported by the National Natural Science Foundation of China (No. 60072004)
文摘The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm （MCNA） is first introduced, and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio （Rp）. For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.
文摘This paper presents a partition-based Design-for- Test （DFT） technique to reduce the power consumption during scan-based testing. This method is based on partitioning the chip into several independent scan domains. By enabling the scan domains alternatively, only a fraction of the entire chip will be active at the same time, leading to low power consumption during test. Therefore, it will significantly reduce the possibility of Electronic Migration and Overheating. In order to prevent the drop of fault coverage, wrappers on the boundaries between scan domains are employed. This paper also presents a detailed design flow based on Electronics Design Automation （EDA） tools from Synopsy~ to implement the proposed test structure. The proposed DFT method is experimented on a state-of-theart System-ou-chips （SOC）. The simulation results show a significant reduction in both average and peak power dissipation without sacrificing the fault coverage and test time. This SOC has been taped out in TSMC and finished the final test m ADVANTEST.
基金supported by the National Natural Science Foundation of China under Grant No. 61176025 and No. 61006027the Fundamental Research Funds for the Central Universities under Grant No.ZYGX2012J003+1 种基金National Laboratory of Analogue Integrated Circuit Grants under Grant No. 9140C0901101002 and No. 9140C0901101003New Century Excellent Talents Program under Grant No.NCET-10-0297
文摘Power dissipation has become one of the key optimization conditions in logic design on field programmable gate arrays （FPGAs）, thus the power estimation is necessary for logic design optimization. Nowadays, signal activity data created by logic simulation based on test vectors is essential to be used to determine the toggle rate of each signals and blocks in power estimation tools provided by field programmable gate array （FPGA） electronic design automation （EDA） tools. The accuracy of power estimation highly depends on the quality of test vectors, especially, pattern coverage. As probability distribution can describe the uncertainty signals, this work provides an algorithm which can estimate FPGAs power more effectively and accurately by using signal probability distribution rather than test vectors.
基金Project(51301143)supported by the National Natural Science Foundation of ChinaProject(2014M560727)supported by the National Postdoctoral Foundation of China+1 种基金Project(2015GZ0228)supported by the Sichuan Province Science-Technology Support Plan,ChinaProject(2682014CX001)supported by the Science and Technology Innovation Project of SWJTU University,China
文摘Flow behaviors of spray forming low solvus high refractory (LSHR) alloy were investigated using hot compression tests performed on a Gleeble?3500 thermal mechanical simulator at temperatures of 1020?1150 °C and strain rates of 0.0003?1.0 s?1. The constitutive equation was established, power dissipation (η) maps and hot processing maps were plotted. The microstructure evolution and dislocation distribution of domains with different values of η in power dissipation maps were also observed. The results show that the flow stress increases with decreasing temperature and increasing strain rate. The activation energy of the spray forming LSHR alloy is 1243.86 kJ/mol. When the value of η is 0.36 at the strain of 0.5, the domain in the processing map shows characteristics of typical dynamic recrystallization (DRX) and low dislocation density. According to the microstructure evolution and processing maps, the optimum processing condition for good hot workability of spray forming LSHR alloy can be summed up as:temperature range 1110?1150 °C; strain rate range 0.01?0.3 s?1.
文摘The mechanical behavior of 2124 Al alloy produced by powder metallurgy was investigated with compression test at different temperatures and strain rates. The tests were performed in the temperature range of 300℃～500℃ and at strain rates from 0.001 s^-1 to 1.0 s^-1. The compression flow curves exhibited an initial sharp increase with strain, followed by monotonous hardening. The maximum stress decreased with decreasing strain rate and increasing temperature. The hot deformation characteristics of the material were studied using processing maps. The domain of safety and unsafe regime were identified and validated through microstructural examination.
基金This work was supported by the Shaanxi Key Research and Development Program(No.S2017-ZDYF-ZDXM-GY-0115)Natural Science Basic Research Plan in Shaanxi Province of China(No.2017JM5010)Fundamental Research Funds for the Central Universities of China(No.3102019ZX004).
文摘Isothermal compression tests of as-forged 30Si2MnCrMoVE low-alloying ultra-high-strength steel were carried out on a Gleeble 3500 thermal simulator at the deformation temperatures of 950-1150℃and strain rates of 0.01-10 s^−1.Based on the classical stress-dislocation density relationship and the kinematics of the dynamic recrystallization,the constitutive equations of the work hardening dynamical recovery period and dynamical recrystallization period were developed by using the work hardening curve and Avrami equation,which shows good agreement with the experimental value.Processing maps at the strain of 0.90 were constructed based on dynamic material model and were analyzed combined with microstructure observation under different conditions.The optimum parameter based on the processing maps was obtained and verified by a supplementary experiment.The power dissipation maps and instability maps at strains of 0.05-0.90 were also constructed,and the evolution law was analyzed in detail.The established constitutive equation and hot processing maps can provide some guidance for hot working process.
基金financially supported by the High Technology Research and Development Program of China (No.SS2012AA030801)the National Basic Research Development Program of China (No.2010CB631203)the Common Technical Research Aircraft Key Component Forming (No.2012ZX04010-081)
文摘The hot deformation behavior of IN706 has been investigated by means of hot compression tests in the temperature range of 900-1150℃ and strain rate range of 0.001-1 s^-1. The constitutive equation was developed on the basis of experimental data. Power dissipation efficiency （η） and instability parameter （4） maps were evaluated using the principles of the dynamic material model. Furthermore, the EBSD microstructure analysis was performed for validation, revealing that η was closely associated with the mechanism of dynamic recrystallization （DRX）. Microstructure transition map was composed of contour plots of η, 4, and DRX. The DRX domain zones and instable zones were identified in the processing map and were classified based on η. In a view of microstructure refinement and workability improvement, the optimum processing should be selected in the temperature range of 970-1025 ~C and the strain rate range of 0.08-0.01 s^-1.
基金supported by the National Natural Science Foundation of China (Grant No.12072114)the National Key Research and Development Plan (Grant No.2020YFB1709401)the Guangdong Provincial Key Laboratory of Modern Civil Engineering Technology (2021B1212040003).
文摘In this paper,we consider solving the topology optimization for steady-state incompressibleNavier-Stokes problems via a new topology optimization method called parameterized level set method,which can maintain a relatively smooth level set function with a local optimality condition.The objective of topology optimization is tond an optimal conguration of theuid and solid materials that minimizes power dissipation under a prescribeduid volume fraction constraint.An articial friction force is added to the Navier-Stokes equations to apply the no-slip boundary condition.Although a great deal of work has been carried out for topology optimization ofuidow in recent years,there are few researches on the topology optimization ofuidow with physical body forces.To simulate theuidow in reality,the constant body force(e.g.,gravity)is considered in this paper.Several 2D numerical examples are presented to discuss the relationships between the proposed method with Reynolds number and initial design,and demonstrate the feasibility and superiority of the proposed method in dealing with unstructuredmesh problems.Three 3D numerical examples demonstrate the proposedmethod is feasible in three-dimensional.
基金supported by the National Natural Science Foundation of the China (Grant Nos 60676009 and 60776034)the Doctor Foundation of Ministry of Education of China (Grant No 20050701015)the National Outstanding Young Scientist Foundation of China (Grant No 60725415)
文摘Repeater optimization is the key for SOC （System on Chip） interconnect delay design. This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines. It also presents Lagrangian function to find the number of repeaters and their sizes required for minimizing area and power overhead with target delay constraint. Based on the 65 nanometre CMOS technology, the computed results of the intermediate and global lines show that the proposed model can significantly reduce area and power of interconnected lines, and the better performance will be achieved with the longer line. The results compared with the reference paper demonstrate the validity of this model. It can be integrated into repeater design methodology and CAD （computer aided design） tool for interconnect planning in nanometre SOC.
基金The authors are grateful for the financial support from the National Natural Science Foundation of China(General Project,Grant No.51674004).
文摘The true stress–true strain curves of 25Cr2Ni4MoVA steel were obtained by uniaxial compression experiments at 850–1200℃ in the strain rate range of 0.001–10.0 s^(−1).And the dynamic continuous cooling transformation curves were obtained at the cooling rate range of 0.5–15.0℃ s^(−1) from the austenitization temperature of 1000℃ to the room temperature by pre-strain of 0.2 as well.The power dissipation map and the dynamic continuous cooling transformation diagram were constructed based on the data provided by these curves.Compared with the optical micrographs of the compressed samples,the full dynamic recrystallization region is located between 1000 and 1200℃ and at the strain rate range from 0.01 to 10.0 s^(−1) with the power dissipation efficiency not less than 0.33.In the full dynamic recrystallization region,the power dissipation efficiency increases and the dynamic recrystallization activation energy decreases with the temperature increasing.With the strain rate decreasing,the power dissipation efficiency increases firstly and then starts to decrease as the strain rate is less than 0.1 s^(−1),and dynamic recrystallization activation energy changes on the contrary.According to the dynamic continuous cooling transformation diagram,slow cooling is a better way for the hot-deformed piece with large size or complex shape to avoid cracking as the temperature of the piece is lower than 400℃,and different cooling ways can be used for the hot-deformed piece with small size and simple shapes to obtain certain microstructure and meet good compressive properties.
基金National Key Research and Development Program of China(2016YFC0401903)National Natural Science Foundation of China(51722906,51679159,51509179)Tianjin Research Program of Application Foundation and Advanced Technology(15JCYBTC21800)
文摘The classification of tropical cyclones(TCs) is significant to obtaining their temporal and spatial variation characteristics in the context of dramatic-changing global climate. A new TCs clustering method by using K-means clustering algorithm with nine physical indexes is proposed in the paper. Each TC is quantified into an 11-dimensional vector concerning trajectory attributes, time attributes and power attributes. Two recurving clusters(cluster A and E)and three straight-moving clusters(cluster B, C and D) are categorized from the TC best-track dataset of the western North Pacific(WNP) over the period of 1949-2013, and TCs' properties have been analyzed and compared in different aspects. The calculation results of coefficient variation(CV) and Nash-Sutcliffe efficiency(NSE) reveal a high level of intra-cluster cohesiveness and inter-cluster divergence, which means that the physical index system could serve as a feasible method of TCs classification. The clusters are then analyzed in terms of trajectory, lifespan, seasonality, trend,intensity and Power Dissipation Index(PDI). The five classified clusters show distinct features in TCs' temporal and spatial development discipline. Moreover, each cluster has its individual motion pattern, variation trend, influence region and impact degree.
