The downlink energy-efficient transmission schedule with non-ideal circuit power over Wreless networks involving a single transmitter and multiple receivers was investigated. According to the special structure of the ...The downlink energy-efficient transmission schedule with non-ideal circuit power over Wreless networks involving a single transmitter and multiple receivers was investigated. According to the special structure of the problem, a novel algorithm called OOSCPMR （the optimal offine scheduling with non-ideal circuit power for multi-receivers） is proposed, and the optimal offine solutions to optimize the energy- efficient transmission policy are found. The packets to be transmitted can be divided into two types where one type of packet is determined to be transmitted using the enrgy- efficient tansmission time, and the other type of packet is determined by the ID moveright algorithm. Finally, an energy-efficient online schedule is developed based on te proposed OOSCPMR algoriAm. Simulation results show that the optima offline transmission schedule provides te lower bound performance for the online tansmission schedule. The proposed optimal offline and online policy is more energy efficient than the existing schemes tat assume ideal circuit power.展开更多
In the field of energy conversion,the increasing attention on power electronic equipment is fault detection and diagnosis.A power electronic circuit is an essential part of a power electronic system.The state of its i...In the field of energy conversion,the increasing attention on power electronic equipment is fault detection and diagnosis.A power electronic circuit is an essential part of a power electronic system.The state of its internal components affects the performance of the system.The stability and reliability of an energy system can be improved by studying the fault diagnosis of power electronic circuits.Therefore,an algorithm based on adaptive simulated annealing particle swarm optimization(ASAPSO)was used in the present study to optimize a backpropagation(BP)neural network employed for the online fault diagnosis of a power electronic circuit.We built a circuit simulation model in MATLAB to obtain its DC output voltage.Using Fourier analysis,we extracted fault features.These were normalized as training samples and input to an unoptimized BP neural network and BP neural networks optimized by particle swarm optimization(PSO)and the ASAPSO algorithm.The accuracy of fault diagnosis was compared for the three networks.The simulation results demonstrate that a BP neural network optimized with the ASAPSO algorithm has higher fault diagnosis accuracy,better reliability,and adaptability and can more effectively diagnose and locate faults in power electronic circuits.展开更多
The incidence chromatic number of G is the least number of colors such that G has an incidence coloring. It is proved that the incidence chromatic number of Cn^p, the p-th power of the circuit graph, is 2p ＋ 1 if and...The incidence chromatic number of G is the least number of colors such that G has an incidence coloring. It is proved that the incidence chromatic number of Cn^p, the p-th power of the circuit graph, is 2p ＋ 1 if and only if n = k（2p ＋ 1）, for other cases： its incidence chromatic number is at most 2p ＋ [r/k] ＋ 2, where n = k（p ＋ 1） ＋ r, k is a positive integer. This upper bound is tight for some cases.展开更多
The power consumption of a variable optical attenuator（VOA） array based on a silica planar lightwave circuit was investigated. The thermal field profile of the device was optimized using the finite-element analysis....The power consumption of a variable optical attenuator（VOA） array based on a silica planar lightwave circuit was investigated. The thermal field profile of the device was optimized using the finite-element analysis. The simulation results showed that the power consumption reduces as the depth of the heat-insulating grooves is deeper, the up-cladding is thinner,the down-cladding is thicker, and the width of the cladding ridge is narrower. The materials component and thickness of the electrodes were also optimized to guarantee the driving voltage under 5 V. The power consumption was successfully reduced to as low as 155 mW at an attenuation of 30 dB in the experiment.展开更多
In order to study the role of printed circuit board(PCB)in high-power LED heat dissipation,a simple model of high-power LED lamp was designed.According to this lamp model,some thermal performances such as thermal resi...In order to study the role of printed circuit board(PCB)in high-power LED heat dissipation,a simple model of high-power LED lamp was designed.According to this lamp model,some thermal performances such as thermal resistances of four types of PCB and the changes of LED junction temperature were tested under three different working currents.The obtained results indicate that LED junction temperature can not be lowered significantly with the decreasing thermal resistance of PCB.However,PCB with low thermal resistance can be matched with smaller volume heat sink,so it is hopeful to reduce the size,weight and cost of LED lamp.展开更多
Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the deriv...Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.展开更多
Recently, resonant AC/DC converter has been accepted by the industry. However, the efficiency will be decreased at light load. So, a novel topology with critical controlling mode combined with resonant ones is propose...Recently, resonant AC/DC converter has been accepted by the industry. However, the efficiency will be decreased at light load. So, a novel topology with critical controlling mode combined with resonant ones is proposed in this paper. The new topology can correspond to a 90 plus percent of power converting. So,a novel topology of an state of-art integrated circuit, which can be used as power management circuit, has been designed based on the above new topology. A simulator which is specific suitable for the power controller has been founded in this work and it has been used for the simulation of the novel architecture and the proposed integrated circuit.展开更多
This paper explores and proposes a design solution of an integrated skip cycle mode （SCM） control circuit with a simple structure. The design is simulated and implemented with XD10H-1.0μm modular DIMOS 650 V proces...This paper explores and proposes a design solution of an integrated skip cycle mode （SCM） control circuit with a simple structure. The design is simulated and implemented with XD10H-1.0μm modular DIMOS 650 V process. In order to meet the requirement of a wide temperature range and high yields of products, the schematic extracted from the layout is simulated with five process corners at 27℃ and 90℃. Simulation results demonstrate that the proposed integrated circuit is immune to noise and achieves skipping cycle control when switching mode power supply （SMPS） works with low load or without load.展开更多
This paper discusses a high efficient parallel circuit simulator for iterative power grid optimization. The simulator is implemented by FPGA. We focus particularly on the following points: 1) Selection of the analysis...This paper discusses a high efficient parallel circuit simulator for iterative power grid optimization. The simulator is implemented by FPGA. We focus particularly on the following points: 1) Selection of the analysis method for power grid optimization, the proposed simulator introduces hardware-oriented fixed point arithmetic instead of floating point arithmetic. It accomplishes the high accuracy by selecting appropriate time step of the simulation;2) The simulator achieves high speed simulation by developing dedicated hardware and adopting parallel processing. Experiments prove that the proposed simulator using 80 MHz FPGA and eight parallel processing achieves 35 times faster simulation than software processing with 2.8 GHz CPU while maintaining almost same accuracy in comparison with SPICE simulation.展开更多
Isolated power converters have emerged as an active research topic in power integrated circuit(IC)design.Reflecting this growing interest,ISSCC 2025 has featured a dedicated session on"Isolated Power and Gate Dri...Isolated power converters have emerged as an active research topic in power integrated circuit(IC)design.Reflecting this growing interest,ISSCC 2025 has featured a dedicated session on"Isolated Power and Gate Drivers".These converters enable safe and reliable power delivery across voltage domains and are widely used in renewable energy,electric vehicles,and telecommunications.Galvanic isolation prevents surge currents and ground loop issues in harsh high-voltage environments.As demand grows for compact,efficient,and high–power-density solutions,fully integrated architectures featuring on-chip transformers are increasingly favored over traditional module-based designs,offering>5 kV isolation with a smaller footprint and lower system cost[1].展开更多
The ?method is used in this paper to calculate the leakage magnetic field of SSZ11-50000/110 Power transformer, and by which the structures’ influences to the main leakage flux are analyzed. Through the combination o...The ?method is used in this paper to calculate the leakage magnetic field of SSZ11-50000/110 Power transformer, and by which the structures’ influences to the main leakage flux are analyzed. Through the combination of the product and TEAM Problem 21B, the surface impedance method shows its great advantage in the calculation of eddy current loss.展开更多
In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gat...In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.展开更多
With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip （SoC）. Dynamic voltage scaling （DVS）...With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip （SoC）. Dynamic voltage scaling （DVS） is an effective method for low-power designs. However, traditional DVS methods have two deficiencies. First, they have a conservative safety margin which is not necessary for most of the time. Second, they are exclusively concerned with the critical stage and ignore the significant potential free slack time of the noncritical stage. These factors lead to a large amount of power waste. In this paper, a novel pipeline structure with ultra-low power consumption is proposed. It cuts off the safety margin and takes use of the noncritical stages at the same time. A prototype pipeline is designed in 0.13 μm technology and analyzed. The result shows that a large amount of energy can be saved by using this structure. Compared with the fixed voltage case, 50% of the energy can be saved, and with respect to the traditional adaptive voltage scaling design, 37.8% of the energy can be saved.展开更多
The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The t...The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.展开更多
基金The National Natural Science Foundation of China(No.61571123,61521061)the National Science and Technology Major Project(No.2016ZX03001011-005)+1 种基金the Research Fund of National Mobile Communications Research Laboratory of Southeast University(No.2017A03)Qing Lan Project
文摘The downlink energy-efficient transmission schedule with non-ideal circuit power over Wreless networks involving a single transmitter and multiple receivers was investigated. According to the special structure of the problem, a novel algorithm called OOSCPMR （the optimal offine scheduling with non-ideal circuit power for multi-receivers） is proposed, and the optimal offine solutions to optimize the energy- efficient transmission policy are found. The packets to be transmitted can be divided into two types where one type of packet is determined to be transmitted using the enrgy- efficient tansmission time, and the other type of packet is determined by the ID moveright algorithm. Finally, an energy-efficient online schedule is developed based on te proposed OOSCPMR algoriAm. Simulation results show that the optima offline transmission schedule provides te lower bound performance for the online tansmission schedule. The proposed optimal offline and online policy is more energy efficient than the existing schemes tat assume ideal circuit power.
基金supported by the 2022 Project for Improving the Basic Research Ability of Young and Middle-aged Teachers in Guangxi Universities(Grant No.2022KY0209).
文摘In the field of energy conversion,the increasing attention on power electronic equipment is fault detection and diagnosis.A power electronic circuit is an essential part of a power electronic system.The state of its internal components affects the performance of the system.The stability and reliability of an energy system can be improved by studying the fault diagnosis of power electronic circuits.Therefore,an algorithm based on adaptive simulated annealing particle swarm optimization(ASAPSO)was used in the present study to optimize a backpropagation(BP)neural network employed for the online fault diagnosis of a power electronic circuit.We built a circuit simulation model in MATLAB to obtain its DC output voltage.Using Fourier analysis,we extracted fault features.These were normalized as training samples and input to an unoptimized BP neural network and BP neural networks optimized by particle swarm optimization(PSO)and the ASAPSO algorithm.The accuracy of fault diagnosis was compared for the three networks.The simulation results demonstrate that a BP neural network optimized with the ASAPSO algorithm has higher fault diagnosis accuracy,better reliability,and adaptability and can more effectively diagnose and locate faults in power electronic circuits.
基金Supported by NSFC(10201022,10571124,10726008)Supported by SRCPBMCE(KM200610028002)Supported by BNSF(1012003)
文摘The incidence chromatic number of G is the least number of colors such that G has an incidence coloring. It is proved that the incidence chromatic number of Cn^p, the p-th power of the circuit graph, is 2p ＋ 1 if and only if n = k（2p ＋ 1）, for other cases： its incidence chromatic number is at most 2p ＋ [r/k] ＋ 2, where n = k（p ＋ 1） ＋ r, k is a positive integer. This upper bound is tight for some cases.
基金Project supported by the National High Technology Research and Development Program of China(Grant No.2015AA016902)the National Nature Science Foundation of China(Grant Nos.61435013,61405188,and 61627820)
文摘The power consumption of a variable optical attenuator（VOA） array based on a silica planar lightwave circuit was investigated. The thermal field profile of the device was optimized using the finite-element analysis. The simulation results showed that the power consumption reduces as the depth of the heat-insulating grooves is deeper, the up-cladding is thinner,the down-cladding is thicker, and the width of the cladding ridge is narrower. The materials component and thickness of the electrodes were also optimized to guarantee the driving voltage under 5 V. The power consumption was successfully reduced to as low as 155 mW at an attenuation of 30 dB in the experiment.
基金Special Fund Project of Science and Technology Innovation of Dongli District(21090302)Research Projectof Applied Basic and Front Technologies of Tianjin(10JCZDJC15400)
文摘In order to study the role of printed circuit board(PCB)in high-power LED heat dissipation,a simple model of high-power LED lamp was designed.According to this lamp model,some thermal performances such as thermal resistances of four types of PCB and the changes of LED junction temperature were tested under three different working currents.The obtained results indicate that LED junction temperature can not be lowered significantly with the decreasing thermal resistance of PCB.However,PCB with low thermal resistance can be matched with smaller volume heat sink,so it is hopeful to reduce the size,weight and cost of LED lamp.
基金Supported by the NSF of China (# 69773034) and DARPA under contract # F33615-95-C-1627
文摘Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.
文摘Recently, resonant AC/DC converter has been accepted by the industry. However, the efficiency will be decreased at light load. So, a novel topology with critical controlling mode combined with resonant ones is proposed in this paper. The new topology can correspond to a 90 plus percent of power converting. So,a novel topology of an state of-art integrated circuit, which can be used as power management circuit, has been designed based on the above new topology. A simulator which is specific suitable for the power controller has been founded in this work and it has been used for the simulation of the novel architecture and the proposed integrated circuit.
文摘This paper explores and proposes a design solution of an integrated skip cycle mode （SCM） control circuit with a simple structure. The design is simulated and implemented with XD10H-1.0μm modular DIMOS 650 V process. In order to meet the requirement of a wide temperature range and high yields of products, the schematic extracted from the layout is simulated with five process corners at 27℃ and 90℃. Simulation results demonstrate that the proposed integrated circuit is immune to noise and achieves skipping cycle control when switching mode power supply （SMPS） works with low load or without load.
文摘This paper discusses a high efficient parallel circuit simulator for iterative power grid optimization. The simulator is implemented by FPGA. We focus particularly on the following points: 1) Selection of the analysis method for power grid optimization, the proposed simulator introduces hardware-oriented fixed point arithmetic instead of floating point arithmetic. It accomplishes the high accuracy by selecting appropriate time step of the simulation;2) The simulator achieves high speed simulation by developing dedicated hardware and adopting parallel processing. Experiments prove that the proposed simulator using 80 MHz FPGA and eight parallel processing achieves 35 times faster simulation than software processing with 2.8 GHz CPU while maintaining almost same accuracy in comparison with SPICE simulation.
基金supported in part by the National Natural Science Foundation of China under Grant U23A20353.
文摘Isolated power converters have emerged as an active research topic in power integrated circuit(IC)design.Reflecting this growing interest,ISSCC 2025 has featured a dedicated session on"Isolated Power and Gate Drivers".These converters enable safe and reliable power delivery across voltage domains and are widely used in renewable energy,electric vehicles,and telecommunications.Galvanic isolation prevents surge currents and ground loop issues in harsh high-voltage environments.As demand grows for compact,efficient,and high–power-density solutions,fully integrated architectures featuring on-chip transformers are increasingly favored over traditional module-based designs,offering>5 kV isolation with a smaller footprint and lower system cost[1].
文摘The ?method is used in this paper to calculate the leakage magnetic field of SSZ11-50000/110 Power transformer, and by which the structures’ influences to the main leakage flux are analyzed. Through the combination of the product and TEAM Problem 21B, the surface impedance method shows its great advantage in the calculation of eddy current loss.
文摘In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.
基金supported by the Important National S&T Special Project of China under Grant No.2011ZX01034-002-001-2the Fundamental Research Funds for the Central Universities under Grant No.ZYGX2009J026
文摘With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip （SoC）. Dynamic voltage scaling （DVS） is an effective method for low-power designs. However, traditional DVS methods have two deficiencies. First, they have a conservative safety margin which is not necessary for most of the time. Second, they are exclusively concerned with the critical stage and ignore the significant potential free slack time of the noncritical stage. These factors lead to a large amount of power waste. In this paper, a novel pipeline structure with ultra-low power consumption is proposed. It cuts off the safety margin and takes use of the noncritical stages at the same time. A prototype pipeline is designed in 0.13 μm technology and analyzed. The result shows that a large amount of energy can be saved by using this structure. Compared with the fixed voltage case, 50% of the energy can be saved, and with respect to the traditional adaptive voltage scaling design, 37.8% of the energy can be saved.
基金Supported by the Guangdong Provincial Natural Science Foundation of China(2014A030313441)the Guangzhou Science and Technology Project(201510010169)+1 种基金the Guangdong Province Science and Technology Project(2016B090918071,2014A040401076)the National Natural Science Foundation of China(61072028)
文摘The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.
