A dual-band filtering push‒pull power amplifier(PA)with a large frequency ratio is presented in this paper.The proposed filtering power dividing/combining network is based on a hybrid-mode filtering balun using micros...A dual-band filtering push‒pull power amplifier(PA)with a large frequency ratio is presented in this paper.The proposed filtering power dividing/combining network is based on a hybrid-mode filtering balun using microstrip line(MSL)and substrate integrated waveguide(SIW).The MSL filtering balun operates in the S-band,with a frequency range of 2.6‒2.86 GHz.Meanwhile,the SIW filtering balun is designed for Ku-band operation,covering a frequency range of 13‒13.65 GHz.Under these conditions,the prototype is capable of attaining a frequency ratio as high as five times the original value.Due to the inherent differential characteristic of the hybrid-mode filtering balun with a large frequency ratio,the proposed push‒pull PA not only realizes filtering functionality but also achieves second-harmonic suppression.To validate the designed concept,the proposed prototype has been designed,fabricated,and measured.Measurement results demonstrate that the proposed PA achieves a 7 dB small-signal gain while maintaining out-of-band spurious rejection during active testing.The developed dual-band filtering push‒pull PA delivers excellent performance,with a peak output power of 36.8 dBm at low frequencies and 36 dBm at high frequencies.Moreover,by employing dual-band filtering baluns,the PA inherently suppresses even-order harmonics while simultaneously providing filtering characteristics in both operational bands,which effectively suppresses near-band spurious signals.展开更多
A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performanc...A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performances than previous works. Implemented in standard 0.35μm CMOS technology, our three-stage amplifier achieves 105dB DC gain, 3.3M GBW,68 phase margin, and 2.56V/μs average slew rate under a 150pF capacitive load. All of these are realized with only 40μW power consumption under a 2V power supply,with very small compensation capacitors.展开更多
In this paper,a 5G wideband power amplifier(PA)with bandpass filtering response is synthesized using a bandwidth-extended bandpass filter as the matching network(MN).In this structure,the bandwidth(θ_(C))is defined a...In this paper,a 5G wideband power amplifier(PA)with bandpass filtering response is synthesized using a bandwidth-extended bandpass filter as the matching network(MN).In this structure,the bandwidth(θ_(C))is defined as a variable in the closedform equations provided by the microstrip bandpass filter.It can be extended over a wide range only by changing the characteristic impedances of the structure.Different from the other wideband MNs,the extension of bandwidth does not increase the complexity of the structure(order n is fixed).In addition,based on the bandwidth-extended structure,the wideband design of bandpass filtering PA is not limited to the fixed bandwidth of the specific filter structure.The theoretical analysis of the MN and the design flow of the PA are provided in this design.The fabricated bandpass filtering PA can support almost one-octave bandwidth(2-3.8 GHz),covering the two 5G bands(n41 and n78).The drain efficiency of 47%-60%and output power higher than 40 dBm are measured.Good frequency selectivity in S-parameter measurements can be observed.展开更多
正交时频空(Orthogonal Time Frequency Space,OTFS)调制因其在高速移动场景下优越的抗多普勒频移特性,被视为未来低地球轨道(Low Earth Orbit,LEO)卫星通信的关键候选技术。然而,OTFS信号固有的峰均功率比(Peak-to-Average Power Ratio...正交时频空(Orthogonal Time Frequency Space,OTFS)调制因其在高速移动场景下优越的抗多普勒频移特性,被视为未来低地球轨道(Low Earth Orbit,LEO)卫星通信的关键候选技术。然而,OTFS信号固有的峰均功率比(Peak-to-Average Power Ratio,PAPR)问题,会严重降低卫星高功率放大器(High-Power Amplifier,HPA)的效率,并引入显著的非线性失真,从而恶化误码率(Bit Error Rate,BER)性能。为解决此问题,提出了一种创新的混合自适应削波(Hybrid Adaptive Clipping,HAC)与神经网络预失真(Neural Network Predistortion)的方法——HAC-NNP。自适应削波(Adaptive Clipping,AC)模块根据实时信道质量或业务需求动态调整削波门限,在PAPR抑制和信号原始失真之间取得初步平衡;轻量级的神经网络(Neural Network,NN)预失真器在发射端对削波后的信号进行处理,训练后用于补偿由“削波处理”和“卫星HPA非线性效应”共同引入的复杂失真。仿真结果表明,在典型的LEO卫星信道和HPA非线性模型下,与传统削波方法相比,该HAC-NNP方法在将PAPR降低约3.5 dB的同时,能够显著改善由削波和HPA非线性共同导致的信号失真,将BER性能恢复至接近无HPA非线性影响的理想水平。展开更多
In this article,a graphic design method for broadband Doherty power amplifier(DPA) is proposed based on the basic principle of impedance matching with the help of Smith chart.The proposed graphic method avoids the com...In this article,a graphic design method for broadband Doherty power amplifier(DPA) is proposed based on the basic principle of impedance matching with the help of Smith chart.The proposed graphic method avoids the complex formula derivation in the traditional amplifier circuit design process,and the design process is more simple and intuitive.Besides,it only takes three steps to build the load modulation network(LMN) of two power amplifiers(PA) of the DPA.Besides,a capacitor is used to replace the parasitic parameters of the transistor,and the LMN designed in the two modes is used for exploration and comparison.Further more,the output impedance of the peaking PA is introduced to make the reflection coefficient trajectory on Smith chart lowfrequency dispersion so as to expand the bandwidth of the DPA at the output power back-off(OBO) level.It would not affect the performance of DPA in the saturation(SAT) state.In this way,a broadband DPA can be implemented easily.To validate the proposed design method,a broadband DPA operating from 1.9to 2.6 GHz is designed and measured based on the proposed method.Under the continuous-wave excitation,the fabricated DPA has a 6 dB OBO efficiency of 48%-56% and a SAT efficiency of 64%-73% from 1.75 to 2.45 GHz,and the peak output power is 48.9-49.8 dBm.展开更多
We propose an optimization method based on evolutionary computation for the design of broadband high-efficiency current-biased reverse load-modulation power amplifiers(CB-RLM PAs).First,given the reverse load-modulati...We propose an optimization method based on evolutionary computation for the design of broadband high-efficiency current-biased reverse load-modulation power amplifiers(CB-RLM PAs).First,given the reverse load-modulation characteristics of CB-RLM PAs,a comprehensive objective function is proposed that combines multi-state impedance trajectory constraints with in-band performance deviations.For the saturation and 6 dB power back-off(PBO)states,approximately optimal impedance regions on the Smith chart are derived using impedance constraint circles based on load-pull simulations.These regions are used together with in-band performance deviations(e.g.,saturated efficiency,6 dB PBO efficiency,and saturated output power)for matching network optimization and design.Second,a multi-objective evolutionary algorithm based on decomposition with adaptive weights,neighborhood,and global replacement is integrated with harmonic balance simulations to optimize design parameters and evaluate performance.Finally,to validate the proposed method,a broadband CB-RLM PA operating from 0.6 to 1.8 GHz is designed and fabricated.Measurement results show that the efficiencies at saturation,6 dB PBO,and 8 dB PBO all exceed 43.6%,with saturated output power being maintained at 40.9–41.5 dBm,which confirms the feasibility and effectiveness of the proposed broadband high-efficiency CB-RLM PA optimization and design approach.展开更多
To reduce the number of digital predistortion coefficients, a step memory polynomial （SMP）predistorter is presented. The number of predistortion coefficients is decreased by adjusting the maximum nonlinear order for...To reduce the number of digital predistortion coefficients, a step memory polynomial （SMP）predistorter is presented. The number of predistortion coefficients is decreased by adjusting the maximum nonlinear order for different memory orders in the traditional memory polynomial （MP）predistorter. The proposed SNIP predistorter is identified by an offline learning structure on which the coefficients can be extracted directly from the sampled input and output of a PA. Simulation results show that the SMP predistorter is not tied to a particular PA model and is, therefore, robust. The effectiveness of the SMP predistorter is demonstrated by simulations and experiments on an MP model, a parallel Wiener model, a Wiener-Hammerstein model, a sparsedelay memory polynomial model and a real PA which is fabricated based on the Freescale LDMOSFET MRF21030. Compared with the traditional MP predistorter, the SMP predistorter can reduce the number of coefficients by 60%.展开更多
An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit...An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.展开更多
A novel patterned-SOI LDMOSFET with a silicon window beneath the p-type channel was designed and fabricated for RF power amplifier applications. This novel device has good DC and RF characteristics. It has no kink eff...A novel patterned-SOI LDMOSFET with a silicon window beneath the p-type channel was designed and fabricated for RF power amplifier applications. This novel device has good DC and RF characteristics. It has no kink effect on output performance,an off-state breakdown of up to 13V,and fT = 6GHz at DC bias of Vg = Vd = 3.6V.At 1.5GHz,a power-added efficiency （PAE） of 50% is achieved with an output power of up to 27dBm from this device.展开更多
A novel behavioral model using three-layer time-delay feed-forward neural networks （TDFFNN）is adopted to model radio frequency （RF）power amplifiers exhibiting memory nonlinearities. In order to extract the paramet...A novel behavioral model using three-layer time-delay feed-forward neural networks （TDFFNN）is adopted to model radio frequency （RF）power amplifiers exhibiting memory nonlinearities. In order to extract the parameters, the back- propagation algorithm is applied to train the proposed neural networks. The proposed model is verified by the typical odd- order-only memory polynomial model in simulation, and the performance is compared with different numbers of taped delay lines（TDLs） and perceptrons of the hidden layer. For validating the TDFFNN model by experiments, a digital test bench is set up to collect input and output data of power amplifiers at a 60 × 10^6 sample/s sampling rate. The 3.75 MHz 16-QAM signal generated in the vector signal generator（VSG） is chosen as the input signal, when measuring the dynamic AM/AM and AM/PM characteristics of power amplifiers. By comparisons and analyses, the presented model provides a good performance in convergence, accuracy and efficiency, which is approved by simulation results and experimental results in the time domain and frequency domain.展开更多
Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed wit...Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.展开更多
To compensate for nonlinear distortion introduced by RF power amplifiers （PAs） with memory effects, two correlated models, namely an extended memory polynomial （EMP） model and a memory lookup table （LUT） model, ...To compensate for nonlinear distortion introduced by RF power amplifiers （PAs） with memory effects, two correlated models, namely an extended memory polynomial （EMP） model and a memory lookup table （LUT） model, are proposed for predistorter design. Two adaptive digital predistortion （ADPD） schemes with indirect learning architecture are presented. One adopts the EMP model and the recursive least square （RLS） algorithm, and the other utilizes the memory LUT model and the least mean square （LMS） algorithm. Simulation results demonstrate that the EMP-based ADPD yields the best linearization performance in terms of suppressing spectral regrowth. It is also shown that the ADPD based on memory LUT makes optimum tradeoff between performance and computational complexity.展开更多
This paper presents a brief overview of several promising design technologies for high efficiency silicon-based radio frequency （RF） power amplifiers （PAs） as well as the use of these technologies in mobile broadb...This paper presents a brief overview of several promising design technologies for high efficiency silicon-based radio frequency （RF） power amplifiers （PAs） as well as the use of these technologies in mobile broadband wireless communications. Four important aspects of PA design are addressed in this paper. First, we look at class-E PA design equations and provide an example of a class-E PA that achieves efficiency of 65-70% at 2.4 GHz. Then, we discuss state-of-the-art envelope tracking （ET） design for monolithic wideband RF mobile transmitter applications. A brief overview of Doherty PA design for the next-generation wireless handset applications is then given. Towards the end of the paper, we discuss an inherently broadband and highly efficient class-J PA design targeting future multi-band multi-standard wireless communication protocols.展开更多
In this letter, a novel model is proposed for modeling the nonlinearity and memory effects of power amplifiers. The classical Volterra model is modified through a function of the sum of nonlinearity order with sum of ...In this letter, a novel model is proposed for modeling the nonlinearity and memory effects of power amplifiers. The classical Volterra model is modified through a function of the sum of nonlinearity order with sum of memory length. The parameters of this model can be extracted in digital domain since the model is analyzed based on the envelope signals. The model we proposed enables a substantial reduction in the number of coefficients involved, and with excellent accuracy.展开更多
The vertical position of plasma in the HT-7U Tokamak is inherently unstable. In order to realize active stabilization, the response rate of the high-power high-frequency amplifier feeding the active control coils must...The vertical position of plasma in the HT-7U Tokamak is inherently unstable. In order to realize active stabilization, the response rate of the high-power high-frequency amplifier feeding the active control coils must be fast enough. This paper analyzes the paralleling scheme of the power amplifier through two kinds of control mode. One is the synchronous control; the other is the asynchronous control. Via the comparison of the two kinds of control mode, both of their characteristics are given in the text. At last, the analyzed result is verified by a small power experiment.展开更多
A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN) cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correl...A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN) cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sampleand-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp) sharing is also introduced to decrease the power dissi...展开更多
For high-voltage and high-power Gallium Nitride(GaN)power amplifiers,a drain modulation circuit with rapid rise and fall time is proposed in this paper.To decrease the rise and fall time,the high-side bootstrap drive ...For high-voltage and high-power Gallium Nitride(GaN)power amplifiers,a drain modulation circuit with rapid rise and fall time is proposed in this paper.To decrease the rise and fall time,the high-side bootstrap drive circuit with an auxiliary discharge switch is proposed.The effect of the parasitics is analyzed based on calculation and the parallel bonding is proposed.The storage capacitance of power supply is calculated quantitatively to provide large pulse current.To ensure safe operation of the power amplifier,the circuit topology with the dead-time control and sequential control is proposed.Finally,a prototype is built to verify the drain modulation circuit design.The experiments prove that the rise time and fall time of the output pulse signal are both less than 100 ns.展开更多
Quasi-PID control method that is able to effectively inhibit the inherent tracking error of PI control method is proposed on the basis of a rounded theoretical analysis of a model of switching power amplifiers (SPAs)....Quasi-PID control method that is able to effectively inhibit the inherent tracking error of PI control method is proposed on the basis of a rounded theoretical analysis of a model of switching power amplifiers (SPAs). To avoid the harmful impacts of the circuit parameter variations and the random disturbances on quasi-PID control method, a single neuron is introduced to endow it with self-adaptability. Quasi-PID control method and the single neuron combine with each other perfectly, and their formation is named as single-neuron adaptive quasi-PID control method. Simulation and experimental results show that single-neuron adaptive quasi-PID control method can accurately track both the predictable and the unpredictable waveforms. Quantitative analysis demonstrates that the accuracy of single-neuron adaptive quasi-PID control method is comparable to that of linear power amplifiers (LPAs) and so can fulfill the requirements of some high-accuracy applications, such as protective relay test. Such accuracy is very difficult to be achieved by many modern control methods for converter controls. Compared with other modern control methods, the programming realization of single-neuron adaptive quasi-PID control method is more suitable for real-time applications and realization on low-end microprocessors for its simple structure and lower computational complexity.展开更多
For the advantages of easy realization and rapidly intelligent response,the one-cycle control was applied in five-phase six-leg switching power amplifier for magnetic bearing.This paper improves the one-cycle control ...For the advantages of easy realization and rapidly intelligent response,the one-cycle control was applied in five-phase six-leg switching power amplifier for magnetic bearing.This paper improves the one-cycle control considering resistance voltage drop and derives its mathematical models.The improved algorithm is compared with the former one.The simulation and experimental results show that the improved algorithm can effectively reduce the output current ripple,achieve good tracking of the given current,improve the control accuracy,and verify the effectiveness and superiority of the method.展开更多
基金supported by the National Natural Science Foundation of China(No.62201262)the Fundamental Research Funds for the Central Universities(No.30924010912).
文摘A dual-band filtering push‒pull power amplifier(PA)with a large frequency ratio is presented in this paper.The proposed filtering power dividing/combining network is based on a hybrid-mode filtering balun using microstrip line(MSL)and substrate integrated waveguide(SIW).The MSL filtering balun operates in the S-band,with a frequency range of 2.6‒2.86 GHz.Meanwhile,the SIW filtering balun is designed for Ku-band operation,covering a frequency range of 13‒13.65 GHz.Under these conditions,the prototype is capable of attaining a frequency ratio as high as five times the original value.Due to the inherent differential characteristic of the hybrid-mode filtering balun with a large frequency ratio,the proposed push‒pull PA not only realizes filtering functionality but also achieves second-harmonic suppression.To validate the designed concept,the proposed prototype has been designed,fabricated,and measured.Measurement results demonstrate that the proposed PA achieves a 7 dB small-signal gain while maintaining out-of-band spurious rejection during active testing.The developed dual-band filtering push‒pull PA delivers excellent performance,with a peak output power of 36.8 dBm at low frequencies and 36 dBm at high frequencies.Moreover,by employing dual-band filtering baluns,the PA inherently suppresses even-order harmonics while simultaneously providing filtering characteristics in both operational bands,which effectively suppresses near-band spurious signals.
文摘A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performances than previous works. Implemented in standard 0.35μm CMOS technology, our three-stage amplifier achieves 105dB DC gain, 3.3M GBW,68 phase margin, and 2.56V/μs average slew rate under a 150pF capacitive load. All of these are realized with only 40μW power consumption under a 2V power supply,with very small compensation capacitors.
基金supported by National Natural Science Foundations of China (No.61971052 and No.U20A20203)Key Research and Development Project of Guangdong Province (2020B0101080001)
文摘In this paper,a 5G wideband power amplifier(PA)with bandpass filtering response is synthesized using a bandwidth-extended bandpass filter as the matching network(MN).In this structure,the bandwidth(θ_(C))is defined as a variable in the closedform equations provided by the microstrip bandpass filter.It can be extended over a wide range only by changing the characteristic impedances of the structure.Different from the other wideband MNs,the extension of bandwidth does not increase the complexity of the structure(order n is fixed).In addition,based on the bandwidth-extended structure,the wideband design of bandpass filtering PA is not limited to the fixed bandwidth of the specific filter structure.The theoretical analysis of the MN and the design flow of the PA are provided in this design.The fabricated bandpass filtering PA can support almost one-octave bandwidth(2-3.8 GHz),covering the two 5G bands(n41 and n78).The drain efficiency of 47%-60%and output power higher than 40 dBm are measured.Good frequency selectivity in S-parameter measurements can be observed.
基金National Natural Science Foundation of China (No. 62001061)。
文摘In this article,a graphic design method for broadband Doherty power amplifier(DPA) is proposed based on the basic principle of impedance matching with the help of Smith chart.The proposed graphic method avoids the complex formula derivation in the traditional amplifier circuit design process,and the design process is more simple and intuitive.Besides,it only takes three steps to build the load modulation network(LMN) of two power amplifiers(PA) of the DPA.Besides,a capacitor is used to replace the parasitic parameters of the transistor,and the LMN designed in the two modes is used for exploration and comparison.Further more,the output impedance of the peaking PA is introduced to make the reflection coefficient trajectory on Smith chart lowfrequency dispersion so as to expand the bandwidth of the DPA at the output power back-off(OBO) level.It would not affect the performance of DPA in the saturation(SAT) state.In this way,a broadband DPA can be implemented easily.To validate the proposed design method,a broadband DPA operating from 1.9to 2.6 GHz is designed and measured based on the proposed method.Under the continuous-wave excitation,the fabricated DPA has a 6 dB OBO efficiency of 48%-56% and a SAT efficiency of 64%-73% from 1.75 to 2.45 GHz,and the peak output power is 48.9-49.8 dBm.
基金supported by the National Natural Science Foundation of China(Nos.62171204,62171129,62001192).
文摘We propose an optimization method based on evolutionary computation for the design of broadband high-efficiency current-biased reverse load-modulation power amplifiers(CB-RLM PAs).First,given the reverse load-modulation characteristics of CB-RLM PAs,a comprehensive objective function is proposed that combines multi-state impedance trajectory constraints with in-band performance deviations.For the saturation and 6 dB power back-off(PBO)states,approximately optimal impedance regions on the Smith chart are derived using impedance constraint circles based on load-pull simulations.These regions are used together with in-band performance deviations(e.g.,saturated efficiency,6 dB PBO efficiency,and saturated output power)for matching network optimization and design.Second,a multi-objective evolutionary algorithm based on decomposition with adaptive weights,neighborhood,and global replacement is integrated with harmonic balance simulations to optimize design parameters and evaluate performance.Finally,to validate the proposed method,a broadband CB-RLM PA operating from 0.6 to 1.8 GHz is designed and fabricated.Measurement results show that the efficiencies at saturation,6 dB PBO,and 8 dB PBO all exceed 43.6%,with saturated output power being maintained at 40.9–41.5 dBm,which confirms the feasibility and effectiveness of the proposed broadband high-efficiency CB-RLM PA optimization and design approach.
基金The National High Technology Research and Development Program of China (863 Program) (No.2008AA01Z211)the Project of Industry-Academia-Research Demonstration Base of Education Ministry of Guangdong Province (No.2007B090200012)
文摘To reduce the number of digital predistortion coefficients, a step memory polynomial （SMP）predistorter is presented. The number of predistortion coefficients is decreased by adjusting the maximum nonlinear order for different memory orders in the traditional memory polynomial （MP）predistorter. The proposed SNIP predistorter is identified by an offline learning structure on which the coefficients can be extracted directly from the sampled input and output of a PA. Simulation results show that the SMP predistorter is not tied to a particular PA model and is, therefore, robust. The effectiveness of the SMP predistorter is demonstrated by simulations and experiments on an MP model, a parallel Wiener model, a Wiener-Hammerstein model, a sparsedelay memory polynomial model and a real PA which is fabricated based on the Freescale LDMOSFET MRF21030. Compared with the traditional MP predistorter, the SMP predistorter can reduce the number of coefficients by 60%.
文摘An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.
文摘A novel patterned-SOI LDMOSFET with a silicon window beneath the p-type channel was designed and fabricated for RF power amplifier applications. This novel device has good DC and RF characteristics. It has no kink effect on output performance,an off-state breakdown of up to 13V,and fT = 6GHz at DC bias of Vg = Vd = 3.6V.At 1.5GHz,a power-added efficiency （PAE） of 50% is achieved with an output power of up to 27dBm from this device.
基金The National Natural Science Foundation of China(No.60621002)the National High Technology Research and Development Pro-gram of China(863 Program)(No.2007AA01Z2B4).
文摘A novel behavioral model using three-layer time-delay feed-forward neural networks （TDFFNN）is adopted to model radio frequency （RF）power amplifiers exhibiting memory nonlinearities. In order to extract the parameters, the back- propagation algorithm is applied to train the proposed neural networks. The proposed model is verified by the typical odd- order-only memory polynomial model in simulation, and the performance is compared with different numbers of taped delay lines（TDLs） and perceptrons of the hidden layer. For validating the TDFFNN model by experiments, a digital test bench is set up to collect input and output data of power amplifiers at a 60 × 10^6 sample/s sampling rate. The 3.75 MHz 16-QAM signal generated in the vector signal generator（VSG） is chosen as the input signal, when measuring the dynamic AM/AM and AM/PM characteristics of power amplifiers. By comparisons and analyses, the presented model provides a good performance in convergence, accuracy and efficiency, which is approved by simulation results and experimental results in the time domain and frequency domain.
文摘Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.
文摘To compensate for nonlinear distortion introduced by RF power amplifiers （PAs） with memory effects, two correlated models, namely an extended memory polynomial （EMP） model and a memory lookup table （LUT） model, are proposed for predistorter design. Two adaptive digital predistortion （ADPD） schemes with indirect learning architecture are presented. One adopts the EMP model and the recursive least square （RLS） algorithm, and the other utilizes the memory LUT model and the least mean square （LMS） algorithm. Simulation results demonstrate that the EMP-based ADPD yields the best linearization performance in terms of suppressing spectral regrowth. It is also shown that the ADPD based on memory LUT makes optimum tradeoff between performance and computational complexity.
文摘This paper presents a brief overview of several promising design technologies for high efficiency silicon-based radio frequency （RF） power amplifiers （PAs） as well as the use of these technologies in mobile broadband wireless communications. Four important aspects of PA design are addressed in this paper. First, we look at class-E PA design equations and provide an example of a class-E PA that achieves efficiency of 65-70% at 2.4 GHz. Then, we discuss state-of-the-art envelope tracking （ET） design for monolithic wideband RF mobile transmitter applications. A brief overview of Doherty PA design for the next-generation wireless handset applications is then given. Towards the end of the paper, we discuss an inherently broadband and highly efficient class-J PA design targeting future multi-band multi-standard wireless communication protocols.
文摘In this letter, a novel model is proposed for modeling the nonlinearity and memory effects of power amplifiers. The classical Volterra model is modified through a function of the sum of nonlinearity order with sum of memory length. The parameters of this model can be extracted in digital domain since the model is analyzed based on the envelope signals. The model we proposed enables a substantial reduction in the number of coefficients involved, and with excellent accuracy.
基金The project supported by the National Meg-Science Engineering Project of Chinese Goverment
文摘The vertical position of plasma in the HT-7U Tokamak is inherently unstable. In order to realize active stabilization, the response rate of the high-power high-frequency amplifier feeding the active control coils must be fast enough. This paper analyzes the paralleling scheme of the power amplifier through two kinds of control mode. One is the synchronous control; the other is the asynchronous control. Via the comparison of the two kinds of control mode, both of their characteristics are given in the text. At last, the analyzed result is verified by a small power experiment.
基金Supported by National Natural Science Foundation of China (No.60806010,No.60976030)Tianjin Innovation Special Funds for Science and Technology (No.05FZZDGX00200)
文摘A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN) cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sampleand-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp) sharing is also introduced to decrease the power dissi...
基金supported by the Pri⁃mary Research&Development Plan of Jiangsu Province(Nos.BE2022070,BE2022070-2).
文摘For high-voltage and high-power Gallium Nitride(GaN)power amplifiers,a drain modulation circuit with rapid rise and fall time is proposed in this paper.To decrease the rise and fall time,the high-side bootstrap drive circuit with an auxiliary discharge switch is proposed.The effect of the parasitics is analyzed based on calculation and the parallel bonding is proposed.The storage capacitance of power supply is calculated quantitatively to provide large pulse current.To ensure safe operation of the power amplifier,the circuit topology with the dead-time control and sequential control is proposed.Finally,a prototype is built to verify the drain modulation circuit design.The experiments prove that the rise time and fall time of the output pulse signal are both less than 100 ns.
文摘Quasi-PID control method that is able to effectively inhibit the inherent tracking error of PI control method is proposed on the basis of a rounded theoretical analysis of a model of switching power amplifiers (SPAs). To avoid the harmful impacts of the circuit parameter variations and the random disturbances on quasi-PID control method, a single neuron is introduced to endow it with self-adaptability. Quasi-PID control method and the single neuron combine with each other perfectly, and their formation is named as single-neuron adaptive quasi-PID control method. Simulation and experimental results show that single-neuron adaptive quasi-PID control method can accurately track both the predictable and the unpredictable waveforms. Quantitative analysis demonstrates that the accuracy of single-neuron adaptive quasi-PID control method is comparable to that of linear power amplifiers (LPAs) and so can fulfill the requirements of some high-accuracy applications, such as protective relay test. Such accuracy is very difficult to be achieved by many modern control methods for converter controls. Compared with other modern control methods, the programming realization of single-neuron adaptive quasi-PID control method is more suitable for real-time applications and realization on low-end microprocessors for its simple structure and lower computational complexity.
基金supported by the National Science Foundation of China(No.51607096)。
文摘For the advantages of easy realization and rapidly intelligent response,the one-cycle control was applied in five-phase six-leg switching power amplifier for magnetic bearing.This paper improves the one-cycle control considering resistance voltage drop and derives its mathematical models.The improved algorithm is compared with the former one.The simulation and experimental results show that the improved algorithm can effectively reduce the output current ripple,achieve good tracking of the given current,improve the control accuracy,and verify the effectiveness and superiority of the method.
