We present an experimental study on tilt-tip（TT） and phase-locking（PL） control in a coherent beam combination（CBC） system of adaptive fiber laser array.The TT control is performed using the adaptive fiber-optics...We present an experimental study on tilt-tip（TT） and phase-locking（PL） control in a coherent beam combination（CBC） system of adaptive fiber laser array.The TT control is performed using the adaptive fiber-optics collimator（AFOC）,and the PL control is realized by the phase modulator（PM）.Cascaded and simultaneous controls of TT and PL using stochastic parallel gradient descent（SPGD） algorithm are investigated in this paper.Two-fiber-laser-,four-fiber-laser-,and six-fiber-laser-arrays are employed to study the TT and PL control.In the cascaded control system,only one high-speed CMOS camera is used to collect beam data and a computer is used as the controller.In a simultaneous control system one high-speed CMOS camera and one photonic detector（PD） are employed,and a computer and a control circuit based on field programmable gate array（FPGA） are used as the controllers.Experimental results reveal that both cascaded and simultaneous controls of TT using AFOC and PL using PM in fiber laser array are feasible and effective.Cascaded control is more effective in static control situation and simultaneous control can be applied to the dynamic control system directly.The control signals of simultaneous PL and TT disturb each other obviously and TT and PL control may compete with each other,so the control effect is limited.展开更多
The mean climatology and the basic characteristics of the ENSO cycle simulated by a coupled model FGCM-1.0 are investigated in this study. Although with some common model biases as in other directly coupled models, FG...The mean climatology and the basic characteristics of the ENSO cycle simulated by a coupled model FGCM-1.0 are investigated in this study. Although with some common model biases as in other directly coupled models, FGCM-1.0 is capable of producing the interannual variability of the tropical Pacific, such as the ENSO phenomenon. The mechanism of the ENSO events in the coupled model can be explained by “delayed oscillator” and “recharge-discharge” hypotheses. Compared to the observations, the simulated ENSO events show larger amplitude with two distinctive types of phase-locking： one with its peak phase-locked to boreal winter and the other to boreal summer. These two types of events have a similar frequency of occurrence, but since the second type of event is seldom observed, it may be related to the biases of the coupled model. Analysis show that the heat content anomalies originate from the central south Pacific in the type of events peaking in boreal summer, which can be attributed to a different background climatology from the normal events. The mechanisms of their evolutions are also discussed.展开更多
The phase-locking process is studied for high-power gyrotron oscillator driven by an external signal. The phase-locking nonlinear differential equations are derived, and the condition of phase-locking is shown and ana...The phase-locking process is studied for high-power gyrotron oscillator driven by an external signal. The phase-locking nonlinear differential equations are derived, and the condition of phase-locking is shown and analyzed. The phase-locking signal can be introduced after gyrotron oscillates into saturation or before it. Two different ways of inputting signal make markable influence on the phase-locking process, this phenomenon is discussed. In this paper, the numerical calculations and analysis are given for gyrotron TE13 mode.展开更多
This paper discusses the chaos and bifurcation for equation x+cosxx+asinx =ebsint. By use of the Melnikov method the conditions to have the chaotic behavior and to have subharmonic oscillations are given.
For Brain-Computer Interface(BCI) systems, improving the Information Transfer Rate(ITR) is a very critical issue. This study focuses on a Steady-State Visually Evoked Potential(SSVEP)-based BCI because of its advantag...For Brain-Computer Interface(BCI) systems, improving the Information Transfer Rate(ITR) is a very critical issue. This study focuses on a Steady-State Visually Evoked Potential(SSVEP)-based BCI because of its advantage of high ITR. Unsupervised Canonical Correlation Analysis(CCA)-based method has been widely employed because of its high efficiency and easy implementation. In a recent study, an ensemble-CCA method based on individual training data was proposed and achieved an excellent performance with ITR of 267 bit/min.A 40-target SSVEP-BCI speller was investigated in this study, using an integration of Minimal-Distance(MD) and Maximal-Phase-locking value(MP) approaches. In the MD approach, a spatial filter is developed to minimize the distance between the training data and the reference sine signal, and in this study, two different types of distance were compared. In the MP approach, a spatial filter is developed to maximize the Phase-Locking Value(PLV)between the training calibration data and the reference sine signal. In addition to the fundamental frequency of stimulation, the harmonics were used to train MD and MP spatial filters, which formed spatial filter banks. The test data epoch was multiplied by the MP and MD spatial filter banks, and the distances and PLVs were extracted as features for recognition. Across 12 subjects with a 0.4 s-data length, the proposed method realized an average classification accuracy and ITR of 93% and 307 bit/min, respectively, which is significantly higher than the current state-of-the-art method. To the best of our knowledge, these results suggest that the proposed method has achieved the highest ITR in SSVEP-BCI studies.展开更多
A comprehensive simulation was performed to better understand the impacts and effects of the additional technical noises on weak-light phase-locking for LISA. The result showed that the phase of the slave laser tracke...A comprehensive simulation was performed to better understand the impacts and effects of the additional technical noises on weak-light phase-locking for LISA. The result showed that the phase of the slave laser tracked well with the received transmitting light under different noise level, and the locking precision was limited by the phase readout noise when the laser frequency noise and clock jitter noise were removed. This result was then confirmed by a benchtop experimental test. The required LISA noise floor was recovered from the simulation which proved the validity of the simulation program. In order to convert the noise function into real time data with random characteristics, an algorism based on Fourier transform was also invented.展开更多
In this paper,a scheme of commonly-resonated extended interaction circuit system based on high order TMn,mode is proposed to lock the phases of two extended interaction oscillators(EIOs)for generating high power at G-...In this paper,a scheme of commonly-resonated extended interaction circuit system based on high order TMn,mode is proposed to lock the phases of two extended interaction oscillators(EIOs)for generating high power at G-band.Two separate EIOs are coupled through a specific single-gap coupling field supported by a designed gap waveguide with length Lg,which form the phase-locked EIOs based on the commonly-resonated system.As a whole system,the system has been focused on with mode analysis based on different single-gap coupling fields,mode hopping,which present the variation of phase difference between the two-beam-wave interactions when changing Lg.To demonstrate the effectiveness of the proposed circuit system in producing the phase locking,we conducted particle-in-cell(PIC)simulations to show that the interesting mode hopping occurs with the phase difference of O and r between the output signals from two output ports,corresponding to the excitation of the TMn mode with different n.Simulation results show that 1)the oscillator can deliver two times of the output power obtained from one single oscillator at 220 GHz,2)the two EIOs can still deliver output signals with phase difference of O and when the currents of the two beams are different or the fabrication errors of the two EIO cavities are taken into account.The proposed scheme is promising in extending to phase locking between multiple EIOs,and generating higher power at millimeter-wave and higher frequencies.展开更多
Sensorless control of switched reluctance motors(SRMs) often requires a hybrid mode combining low-speed pulse injection methods and high-speed model-based estimation.However,pulse injection causes unwanted audible noi...Sensorless control of switched reluctance motors(SRMs) often requires a hybrid mode combining low-speed pulse injection methods and high-speed model-based estimation.However,pulse injection causes unwanted audible noises and torque ripples.This article proposes an enhanced model-based sensorless approach to extend downwards the speed range in which sensorless control can work without injection.An inertial phase-locked loop (IPLL) based on a stator flux observer is introduced for position estimation.Compared to the conventional phase-locked loop scheme,the IPLL offers a more robust disturbance rejection capability and thus reduces the flux model errors at lower speeds.Experimental results substantiate the feasibility of the extended low-speed operation using the model-based sensorless control approach.展开更多
A wide-range and phase-locked Michelson interferometer technique is described. This technique combined with femtosecond laser is used to measure the spectrum of the rare-earth ion Nd：YVO4, which presents very high si...A wide-range and phase-locked Michelson interferometer technique is described. This technique combined with femtosecond laser is used to measure the spectrum of the rare-earth ion Nd：YVO4, which presents very high signal to noise ratio of interferometric intensity output and higher spectral resolution than traditional grating spectrophotometer.展开更多
A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-p...A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.展开更多
CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a bri...CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.展开更多
We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximati...We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.展开更多
A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacr...A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.展开更多
A multimode interference(MMI)structure is designed to simplify the fabrication of quantum cascade laser(QCL)phase-locked arrays.The MMI geometry is optimized with a sufficient output channel distance to accommodate co...A multimode interference(MMI)structure is designed to simplify the fabrication of quantum cascade laser(QCL)phase-locked arrays.The MMI geometry is optimized with a sufficient output channel distance to accommodate conventional photolithography and wet etching process by which power amplifier array is fabricated without using the complicated two-step etching-regrowth or dry etching technique.The far-field pattern with periodically modulated peaks reveals that the beams from the arrays are phase-locked.Furthermore,the frequency tuning performance of the MMI-based phase-locked arrays is studied using the Littrow-configuration external cavity structure.A wavelength tuning range of more than 60 cm^(−1) is demonstrated,which will eventually realize the high power,frequency tunable,large-scale phase-locked arrays,and their application in spectroscopy.展开更多
There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon...There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.展开更多
Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping appro...Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.展开更多
Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to abo...Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.展开更多
High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase...High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.展开更多
A sapphire fibre thermal probe with Cr^3＋ ion-doped end is developed by using the laser heated pedestal growth method. The fluorescence thermal probe offers advantages of compact structure, high performance and abili...A sapphire fibre thermal probe with Cr^3＋ ion-doped end is developed by using the laser heated pedestal growth method. The fluorescence thermal probe offers advantages of compact structure, high performance and ability to withstand high temperature in a detection range from room temperature to 450℃. Based on the fast Fourier transform （FFT）, the fluorescence lifetime is obtained from the tangent function of phase angle of the non-zeroth terms in the FFT result. This method has advantages such as quick calculation, high accuracy and immunity to the background noise. This FFT method is compared with other traditional fitting methods, indicating that the standard deviation of the FFT method is about half of that of the Prony method and about 1/6 of that of the log-fit method. And the FFT method is immune to the background noise involved in a signal. So, the FFT method is an excellent way of processing signals. In addition, a phase-lock amplifier can effectively suppress the noise.展开更多
An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the P...An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the PLL,and,therefore,improves control performances of the disturbed GeCs.Besides,the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions.The unbalanced grid is particularly taken into account for the performance analysis.A tuning approach based on the well-designed PI controller is discussed,which results in a fair comparison with conventional PI-type PLLs.The frequency domain properies are quantitatively analysed with respeet to the control stability and the noises rejection.The frequency domain analysis and simulation results suggesti that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency,while have better ability to atenuate high-frequency measurement noises.The phase margin decreases slightly,but remains acceptable.Finally,experimental tests are conducted with a hybrid power hardwarein-the-loop benchmark,in which balanced/unbalanced cases are both explored.The obtained results prove the effectiveness of ESO based PLLs when applied to the disturbed GeC.展开更多
文摘We present an experimental study on tilt-tip（TT） and phase-locking（PL） control in a coherent beam combination（CBC） system of adaptive fiber laser array.The TT control is performed using the adaptive fiber-optics collimator（AFOC）,and the PL control is realized by the phase modulator（PM）.Cascaded and simultaneous controls of TT and PL using stochastic parallel gradient descent（SPGD） algorithm are investigated in this paper.Two-fiber-laser-,four-fiber-laser-,and six-fiber-laser-arrays are employed to study the TT and PL control.In the cascaded control system,only one high-speed CMOS camera is used to collect beam data and a computer is used as the controller.In a simultaneous control system one high-speed CMOS camera and one photonic detector（PD） are employed,and a computer and a control circuit based on field programmable gate array（FPGA） are used as the controllers.Experimental results reveal that both cascaded and simultaneous controls of TT using AFOC and PL using PM in fiber laser array are feasible and effective.Cascaded control is more effective in static control situation and simultaneous control can be applied to the dynamic control system directly.The control signals of simultaneous PL and TT disturb each other obviously and TT and PL control may compete with each other,so the control effect is limited.
文摘The mean climatology and the basic characteristics of the ENSO cycle simulated by a coupled model FGCM-1.0 are investigated in this study. Although with some common model biases as in other directly coupled models, FGCM-1.0 is capable of producing the interannual variability of the tropical Pacific, such as the ENSO phenomenon. The mechanism of the ENSO events in the coupled model can be explained by “delayed oscillator” and “recharge-discharge” hypotheses. Compared to the observations, the simulated ENSO events show larger amplitude with two distinctive types of phase-locking： one with its peak phase-locked to boreal winter and the other to boreal summer. These two types of events have a similar frequency of occurrence, but since the second type of event is seldom observed, it may be related to the biases of the coupled model. Analysis show that the heat content anomalies originate from the central south Pacific in the type of events peaking in boreal summer, which can be attributed to a different background climatology from the normal events. The mechanisms of their evolutions are also discussed.
文摘The phase-locking process is studied for high-power gyrotron oscillator driven by an external signal. The phase-locking nonlinear differential equations are derived, and the condition of phase-locking is shown and analyzed. The phase-locking signal can be introduced after gyrotron oscillates into saturation or before it. Two different ways of inputting signal make markable influence on the phase-locking process, this phenomenon is discussed. In this paper, the numerical calculations and analysis are given for gyrotron TE13 mode.
基金Project Supported by the National Natural Science Foundation of China
文摘This paper discusses the chaos and bifurcation for equation x+cosxx+asinx =ebsint. By use of the Melnikov method the conditions to have the chaotic behavior and to have subharmonic oscillations are given.
基金supported by the National Natural Science Foundation of China (Nos. 61431007 and 91320202)
文摘For Brain-Computer Interface(BCI) systems, improving the Information Transfer Rate(ITR) is a very critical issue. This study focuses on a Steady-State Visually Evoked Potential(SSVEP)-based BCI because of its advantage of high ITR. Unsupervised Canonical Correlation Analysis(CCA)-based method has been widely employed because of its high efficiency and easy implementation. In a recent study, an ensemble-CCA method based on individual training data was proposed and achieved an excellent performance with ITR of 267 bit/min.A 40-target SSVEP-BCI speller was investigated in this study, using an integration of Minimal-Distance(MD) and Maximal-Phase-locking value(MP) approaches. In the MD approach, a spatial filter is developed to minimize the distance between the training data and the reference sine signal, and in this study, two different types of distance were compared. In the MP approach, a spatial filter is developed to maximize the Phase-Locking Value(PLV)between the training calibration data and the reference sine signal. In addition to the fundamental frequency of stimulation, the harmonics were used to train MD and MP spatial filters, which formed spatial filter banks. The test data epoch was multiplied by the MP and MD spatial filter banks, and the distances and PLVs were extracted as features for recognition. Across 12 subjects with a 0.4 s-data length, the proposed method realized an average classification accuracy and ITR of 93% and 307 bit/min, respectively, which is significantly higher than the current state-of-the-art method. To the best of our knowledge, these results suggest that the proposed method has achieved the highest ITR in SSVEP-BCI studies.
基金supported by the Space Science Research Projects in Advance(Grant No.O930143XM1)the Scientific Equipment Development and Research Project(Grant No.Y231411YB1) of Chinese Academy of Sciences
文摘A comprehensive simulation was performed to better understand the impacts and effects of the additional technical noises on weak-light phase-locking for LISA. The result showed that the phase of the slave laser tracked well with the received transmitting light under different noise level, and the locking precision was limited by the phase readout noise when the laser frequency noise and clock jitter noise were removed. This result was then confirmed by a benchtop experimental test. The required LISA noise floor was recovered from the simulation which proved the validity of the simulation program. In order to convert the noise function into real time data with random characteristics, an algorism based on Fourier transform was also invented.
基金Supported in part by the National Natural Science Foundation of China(62401125)the Natural Science Foundation of Sichuan Province(2023NSFSC1376)the Fundamental Research Funds for the Central Universities(ZYGX2024J008)。
文摘In this paper,a scheme of commonly-resonated extended interaction circuit system based on high order TMn,mode is proposed to lock the phases of two extended interaction oscillators(EIOs)for generating high power at G-band.Two separate EIOs are coupled through a specific single-gap coupling field supported by a designed gap waveguide with length Lg,which form the phase-locked EIOs based on the commonly-resonated system.As a whole system,the system has been focused on with mode analysis based on different single-gap coupling fields,mode hopping,which present the variation of phase difference between the two-beam-wave interactions when changing Lg.To demonstrate the effectiveness of the proposed circuit system in producing the phase locking,we conducted particle-in-cell(PIC)simulations to show that the interesting mode hopping occurs with the phase difference of O and r between the output signals from two output ports,corresponding to the excitation of the TMn mode with different n.Simulation results show that 1)the oscillator can deliver two times of the output power obtained from one single oscillator at 220 GHz,2)the two EIOs can still deliver output signals with phase difference of O and when the currents of the two beams are different or the fabrication errors of the two EIO cavities are taken into account.The proposed scheme is promising in extending to phase locking between multiple EIOs,and generating higher power at millimeter-wave and higher frequencies.
基金supported in part by the National Natural Science Foundation of China 52307069in part by 2024 Tertiary Education Scientific Research Project of Guangzhou Municipal Education Bureau under Grant2024312176in part by the Project of Hetao Shenzhen-Hong Kong Science and Technology Innovation Cooperation Zone under Grant HZQB-KCZYB-2020083。
文摘Sensorless control of switched reluctance motors(SRMs) often requires a hybrid mode combining low-speed pulse injection methods and high-speed model-based estimation.However,pulse injection causes unwanted audible noises and torque ripples.This article proposes an enhanced model-based sensorless approach to extend downwards the speed range in which sensorless control can work without injection.An inertial phase-locked loop (IPLL) based on a stator flux observer is introduced for position estimation.Compared to the conventional phase-locked loop scheme,the IPLL offers a more robust disturbance rejection capability and thus reduces the flux model errors at lower speeds.Experimental results substantiate the feasibility of the extended low-speed operation using the model-based sensorless control approach.
基金ACKNOWLEDGMENTS This work was supported by the National Natural Science Foundation of China （No.60677051 and No.10774193） and the National Key Basic Research Special Foundation （No.G2010CB923204）.
文摘A wide-range and phase-locked Michelson interferometer technique is described. This technique combined with femtosecond laser is used to measure the spectrum of the rare-earth ion Nd：YVO4, which presents very high signal to noise ratio of interferometric intensity output and higher spectral resolution than traditional grating spectrophotometer.
基金The National High Technology Research and Devel-opment Program of China (863Program) (No2001AA312010)
文摘A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.
基金supported by the Pioneer Hundred Talents Program,Chinese Academy of Sciences.
文摘CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.
基金supported by Key Research Program of Frontier Science,Chinese Academy of Sciences(Grant No.QYZDB-SSW-SLH014)the Yong Scientists Fund of the National Natural Science Foundation of China(Grant No.61205143)
文摘We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.
文摘A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.
基金supported by the National Basic Research Program of China(Grant Nos.2018YFA0209103 and 2018YFB2200504)the National Natural Science Foundation of China(Grant Nos.61991430,61774146,61790583,61674144,61774150,and 61805168)+1 种基金the Beijing Municipal Science&Technology Commission,China(Grant No.Z201100004020006)the Key Projects of the Chinese Academy of Sciences(Grant Nos.2018147,YJKYYQ20190002,QYZDJ-SSW-JSC027,and XDB43000000).
文摘A multimode interference(MMI)structure is designed to simplify the fabrication of quantum cascade laser(QCL)phase-locked arrays.The MMI geometry is optimized with a sufficient output channel distance to accommodate conventional photolithography and wet etching process by which power amplifier array is fabricated without using the complicated two-step etching-regrowth or dry etching technique.The far-field pattern with periodically modulated peaks reveals that the beams from the arrays are phase-locked.Furthermore,the frequency tuning performance of the MMI-based phase-locked arrays is studied using the Littrow-configuration external cavity structure.A wavelength tuning range of more than 60 cm^(−1) is demonstrated,which will eventually realize the high power,frequency tunable,large-scale phase-locked arrays,and their application in spectroscopy.
基金supported in part by the National Natural Science Foundation of China(Nos.12005245,12075100,and 11775244)by the Scientific and Technological Innovation Project(No.2020000165)from the Institute of High Energy Physics,Chinese Academy of Sciences+1 种基金partially funded by the Scientific Instrument Development Project of the Chinese Academy of Sciences(No.ZDKYYQ20200007)Youth Innovation Promotion Association of the Chinese Academy of Sciences(No.Y201905).
文摘There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.
基金Project supported by the National Key Research and Development Program of China(Grant Nos.2021YFA0718300 and 2021YFA1400900)the National Natural Science Foundation of China(Grant Nos.11920101004,11934002,and 92365208)+1 种基金Science and Technology Major Project of Shanxi(Grant No.202101030201022)Space Application System of China Manned Space Program.
文摘Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.
基金Supported by the Tsinghua National Laboratory for Information Science and Technology(TNList)Cross-Discipline Foundationthe National Science and Technology Major Project(No.2010ZX03006-003-01)
文摘Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.
基金This work was supported in part by Lodam A/S and in part by the PSO-ELFORSK Program。
文摘High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.
文摘A sapphire fibre thermal probe with Cr^3＋ ion-doped end is developed by using the laser heated pedestal growth method. The fluorescence thermal probe offers advantages of compact structure, high performance and ability to withstand high temperature in a detection range from room temperature to 450℃. Based on the fast Fourier transform （FFT）, the fluorescence lifetime is obtained from the tangent function of phase angle of the non-zeroth terms in the FFT result. This method has advantages such as quick calculation, high accuracy and immunity to the background noise. This FFT method is compared with other traditional fitting methods, indicating that the standard deviation of the FFT method is about half of that of the Prony method and about 1/6 of that of the log-fit method. And the FFT method is immune to the background noise involved in a signal. So, the FFT method is an excellent way of processing signals. In addition, a phase-lock amplifier can effectively suppress the noise.
基金This paper was supported by G2elab,Grenoble INP,University Grenoble Alpes,France and School of Engineering,HES-sO,Valais,Switzerlandfunding provided by Haute Ecole Specialisee de Suisse occidentale(HES-SO)
文摘An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the PLL,and,therefore,improves control performances of the disturbed GeCs.Besides,the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions.The unbalanced grid is particularly taken into account for the performance analysis.A tuning approach based on the well-designed PI controller is discussed,which results in a fair comparison with conventional PI-type PLLs.The frequency domain properies are quantitatively analysed with respeet to the control stability and the noises rejection.The frequency domain analysis and simulation results suggesti that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency,while have better ability to atenuate high-frequency measurement noises.The phase margin decreases slightly,but remains acceptable.Finally,experimental tests are conducted with a hybrid power hardwarein-the-loop benchmark,in which balanced/unbalanced cases are both explored.The obtained results prove the effectiveness of ESO based PLLs when applied to the disturbed GeC.
