针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier...针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放。CSFRA通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗。基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC。该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944μW,其中CSFRA功耗仅为368μW。展开更多
A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor shari...A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.展开更多
For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from h...For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency.Moreover,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+2.Finally,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.展开更多
The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specifi...The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers to perform time-domain behavioral simulations of pipelined analog to digital converters （ADCs）. All the necessary blocks of this specific simulation environment have been implemented using the popular Matlab simulink environment. The purpose of this paper is to present the behavioral models of these blocks taking into account most of the pipelined ADC non-idealities, such as sampling jitter, noise, and operational amplifier parameters （white noise, finite DC gain, finite bandwidth, slew rate, and saturation voltages）. Simulations, using a 10-bit pipelined ADC as a design example, show that in addition to the limits analysis and the electrical features extraction, designers can determine the specifications of the basic blocks in order to meet the given data converter requirements.展开更多
A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sa...A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.展开更多
Power optimization for pipelined analog-to-digital converter(ADC) was studied. Operational principle of pipelined ADC was discussed and noise voltage caused by two important thermal noise sources, sampling switch and ...Power optimization for pipelined analog-to-digital converter(ADC) was studied. Operational principle of pipelined ADC was discussed and noise voltage caused by two important thermal noise sources, sampling switch and amplifier,was quantitatively analyzed. Method used to minimize power and the values under simple model were presented. Power can be saved by making the sampling and feedback capacitors scale down in the pipeline.And the size of capacitors was limited by thermal noise in high resolution ADC.The equivalent circuits of the two important thermal noise sources were established.Thermal noise was optimally distributed among the pipeline stages,and the relationship between scaling factor and closed loop gain was obtained for minimum power dissipation.Typical closed loop gain was 2 or 4 in pipeline ADC, and the corresponding scaling factor was (1.217) and 1.317.These results can serve as useful guidelines for designers to minimize the ADC′s power consumption.展开更多
Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the ...Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.展开更多
This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power const...This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.展开更多
The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things(IoT).In recent years,researchers have ...The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things(IoT).In recent years,researchers have tried to develop hardware-based solutions for the classification of Internet packets.Due to higher throughput and shorter delays,these solutions are considered as a major key to improving the quality of services.Most of these efforts have attempted to implement a software algorithm on the FPGA to reduce the processing time and enhance the throughput.The proposed architectures,however,cannot reach a compromise among power consumption,memory usage,and throughput rate.In view of this,the architecture proposed in this paper contains a pipelinebased micro-core that is used in network processors to classify packets.To this end,three architectures have been implemented using the proposed micro-core.The first architecture performs parallel classification based on header fields.The second one classifies packets in a serial manner.The last architecture is the pipeline-based classifier,which can increase performance by nine times.The proposed architectures have been implemented on an FPGA chip.The results are indicative of a reduction in memory usage as well as an increase in speedup and throughput.The architecture has a power consumption of is 1.294w,and its throughput with a frequency of 233 MHz exceeds 147 Gbps.展开更多
Recent advances in broadband technology have caused forwarding engines to handle pack- ets with over 10 gigabit per second. In this paper, we present a high-speed forwarding pipeline which can finish all of the routin...Recent advances in broadband technology have caused forwarding engines to handle pack- ets with over 10 gigabit per second. In this paper, we present a high-speed forwarding pipeline which can finish all of the routing and forwarding tasks in the way of pipelining. We also establish the analysis model of the pipeline with which one can evaluate some key performance parameters of the forwarding engine such as forwarding rate and forwarding delay. We find that the pipeline is of good scalability and can forward unicast packets up to the speed of 40Gbit/s.展开更多
Fractional motion estimation(FME) improves the video encoding efficiency significantly. However, its high computational complexity limits the real-time processing capability. Therefore, it is a key problem to reduce t...Fractional motion estimation(FME) improves the video encoding efficiency significantly. However, its high computational complexity limits the real-time processing capability. Therefore, it is a key problem to reduce the implementation complexity of FME, especially in hardware design. This paper presents a novel deeply pipelined interpolation architecture of FME for the real-time realization of H.265/HEVC full Ultra-HD video encoder. First, a pipelined interpolation architecture together with an elegant processing order is proposed to deal with different search positions in parallel without pipeline stall and data conflict. Second, interpolation results sharing strategies are exploited among search positions to reduce the memory cost. Finally, the structure of the interpolation filter is further optimized for an area efficient implementation. As a result, the proposed design costs 41 917 slice LUTs on the Xilinx Kintex-7 FPGA platform with a 308 MHz working frequency. The measured throughput reaches a record of 1.238 Gpixels/s, which is sufficient for the real-time encoding of 8192×4320@ 30 fps video.展开更多
In H.264,the computational complexity and memory access of deblocking filter are variable and depend on the video contents. In this paper,a pipelined VLSI architecture of deblocking filter with adaptive dynamic power ...In H.264,the computational complexity and memory access of deblocking filter are variable and depend on the video contents. In this paper,a pipelined VLSI architecture of deblocking filter with adaptive dynamic power is proposed. It avoids redundant computations and memory access by precluding the blocks which can be skipped. And the vertical and horizontal edges are simultaneously processed in an advanced scan order to speed up the decoder. As a result,the dynamic power of the proposed architecture can be reduced (up to about 89%) adaptively for different videos. And the off-chip memory access is improved compared to the previous designs. Moreover,the processing capability of the proposed architecture is very appropriate for real-time deblocking of high-definition television (HDTV,1920× 1080 pixel/frame,30 frame/s video signals) video operation at 38 MHz,which significantly outperforms the previous designs from 1.25 times to 4.8 times.展开更多
A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and it...A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.展开更多
A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the...A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm^2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively.展开更多
A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the prec...A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range （SFDR） of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio （SNDR） of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.展开更多
文摘针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放。CSFRA通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗。基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC。该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944μW,其中CSFRA功耗仅为368μW。
基金supported by the Major National Science & Technology Program of China under Grant No.2012ZX03004004-002National High Technology Research and Development Program of China under Grant No. 2013AA014302
文摘A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.
基金supported in part by the National Key R&D Program of China(No.2019YFB1803400)。
文摘For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency.Moreover,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+2.Finally,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.
文摘The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers to perform time-domain behavioral simulations of pipelined analog to digital converters （ADCs）. All the necessary blocks of this specific simulation environment have been implemented using the popular Matlab simulink environment. The purpose of this paper is to present the behavioral models of these blocks taking into account most of the pipelined ADC non-idealities, such as sampling jitter, noise, and operational amplifier parameters （white noise, finite DC gain, finite bandwidth, slew rate, and saturation voltages）. Simulations, using a 10-bit pipelined ADC as a design example, show that in addition to the limits analysis and the electrical features extraction, designers can determine the specifications of the basic blocks in order to meet the given data converter requirements.
基金The National Science Fund for Creative Re-search Groups( Grant No 60521002 )Shanghai Natural Science Foundation (GrantNo 037062022)
文摘A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.
基金Supported by the Tackling Project of Tianjin Science and Technology Committee (No.033183911).
文摘Power optimization for pipelined analog-to-digital converter(ADC) was studied. Operational principle of pipelined ADC was discussed and noise voltage caused by two important thermal noise sources, sampling switch and amplifier,was quantitatively analyzed. Method used to minimize power and the values under simple model were presented. Power can be saved by making the sampling and feedback capacitors scale down in the pipeline.And the size of capacitors was limited by thermal noise in high resolution ADC.The equivalent circuits of the two important thermal noise sources were established.Thermal noise was optimally distributed among the pipeline stages,and the relationship between scaling factor and closed loop gain was obtained for minimum power dissipation.Typical closed loop gain was 2 or 4 in pipeline ADC, and the corresponding scaling factor was (1.217) and 1.317.These results can serve as useful guidelines for designers to minimize the ADC′s power consumption.
文摘Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.
基金provided by National Chip Implementation Center(CIC)
文摘This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.
文摘The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things(IoT).In recent years,researchers have tried to develop hardware-based solutions for the classification of Internet packets.Due to higher throughput and shorter delays,these solutions are considered as a major key to improving the quality of services.Most of these efforts have attempted to implement a software algorithm on the FPGA to reduce the processing time and enhance the throughput.The proposed architectures,however,cannot reach a compromise among power consumption,memory usage,and throughput rate.In view of this,the architecture proposed in this paper contains a pipelinebased micro-core that is used in network processors to classify packets.To this end,three architectures have been implemented using the proposed micro-core.The first architecture performs parallel classification based on header fields.The second one classifies packets in a serial manner.The last architecture is the pipeline-based classifier,which can increase performance by nine times.The proposed architectures have been implemented on an FPGA chip.The results are indicative of a reduction in memory usage as well as an increase in speedup and throughput.The architecture has a power consumption of is 1.294w,and its throughput with a frequency of 233 MHz exceeds 147 Gbps.
基金Supported by the National High Technology Research and Development Program of China (No.2003AA103510).
文摘Recent advances in broadband technology have caused forwarding engines to handle pack- ets with over 10 gigabit per second. In this paper, we present a high-speed forwarding pipeline which can finish all of the routing and forwarding tasks in the way of pipelining. We also establish the analysis model of the pipeline with which one can evaluate some key performance parameters of the forwarding engine such as forwarding rate and forwarding delay. We find that the pipeline is of good scalability and can forward unicast packets up to the speed of 40Gbit/s.
基金Supported by the Zhejiang Provincial Natural Science Foundation of China(No.LQ15F010001,LY16F020029)the General Research Project of Zhejiang Provincial Education Department(No.Y201430479)
文摘Fractional motion estimation(FME) improves the video encoding efficiency significantly. However, its high computational complexity limits the real-time processing capability. Therefore, it is a key problem to reduce the implementation complexity of FME, especially in hardware design. This paper presents a novel deeply pipelined interpolation architecture of FME for the real-time realization of H.265/HEVC full Ultra-HD video encoder. First, a pipelined interpolation architecture together with an elegant processing order is proposed to deal with different search positions in parallel without pipeline stall and data conflict. Second, interpolation results sharing strategies are exploited among search positions to reduce the memory cost. Finally, the structure of the interpolation filter is further optimized for an area efficient implementation. As a result, the proposed design costs 41 917 slice LUTs on the Xilinx Kintex-7 FPGA platform with a 308 MHz working frequency. The measured throughput reaches a record of 1.238 Gpixels/s, which is sufficient for the real-time encoding of 8192×4320@ 30 fps video.
基金the National Science Foundation of the United States under the East Asia Pacific Program(No.NSS’USA5978)
文摘In H.264,the computational complexity and memory access of deblocking filter are variable and depend on the video contents. In this paper,a pipelined VLSI architecture of deblocking filter with adaptive dynamic power is proposed. It avoids redundant computations and memory access by precluding the blocks which can be skipped. And the vertical and horizontal edges are simultaneously processed in an advanced scan order to speed up the decoder. As a result,the dynamic power of the proposed architecture can be reduced (up to about 89%) adaptively for different videos. And the off-chip memory access is improved compared to the previous designs. Moreover,the processing capability of the proposed architecture is very appropriate for real-time deblocking of high-definition television (HDTV,1920× 1080 pixel/frame,30 frame/s video signals) video operation at 38 MHz,which significantly outperforms the previous designs from 1.25 times to 4.8 times.
文摘A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.
基金supported by the National Natural Science Foundation of China(No.61106027)the 333 Talent Project of Jiangsu Province, China(No.BRA2011115)
文摘A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm^2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively.
基金supported by National Natural Science Foundation of China under grant No.61704161Key Project of Natural Science of Anhui Provincial Department of Education under grant No.KJ2017A396
文摘A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range （SFDR） of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio （SNDR） of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.
