The impacts of remote Coulomb scattering(RCS)on hole mobility in ultra-thin body silicon-on-insulator(UTB SOI)p-MOSFETs at cryogenic temperatures are investigated.The physical models including phonon scattering,surfac...The impacts of remote Coulomb scattering(RCS)on hole mobility in ultra-thin body silicon-on-insulator(UTB SOI)p-MOSFETs at cryogenic temperatures are investigated.The physical models including phonon scattering,surface roughness scattering,and remote Coulomb scatterings are considered,and the results are verified by the experimental results at different temperatures for both bulk(from 300 K to 30 K)and UTB SOI(300 K and 25 K)p-MOSFETs.The impacts of the interfacial trap charges at both front and bottom interfaces on the hole mobility are mainly evaluated for the UTB SOI p-MOSFETs at liquid helium temperature(4.2 K).The results reveal that as the temperature decreases,the RCS due to the interfacial trap charges plays an important role in the hole mobility.展开更多
The hot carrier effects under off- state stress m ode( Vgs=0 ,Vds<0 ) have been investigated on9nm P- MOSFETs with channel length varying from1.0 2 5 μm to0 .5 2 5 μm.Both on- and off- state currents are discuss...The hot carrier effects under off- state stress m ode( Vgs=0 ,Vds<0 ) have been investigated on9nm P- MOSFETs with channel length varying from1.0 2 5 μm to0 .5 2 5 μm.Both on- and off- state currents are discussed. It is found that the off- state leakage current decreases after a higher voltage stressing,which is induced by the charge injection occurred close to the drain junction.However,the leakage current increases after a lower voltage stressing because of the newly generated interface traps.It is also found that the on state saturation current and threshold voltage degrade significantly with the stress tim e,which we believe is due to the charges injected near the gate- drain overlapping region and/ or the stress- induced interface trap generation.The degradation of Idsatcan be ex- pressed as a function of the product of the gate current( Ig) and the num ber of charges injected into the gate oxide ( Qinj) in a simple power law.Finally,a lifetime prediction model based on the degradation of Idsatis proposed.展开更多
Biaxial strain technology is a promising way to improve the mobility of both electrons and holes, while （100） channel direction appears as to be an effective booster of hole mobility in particular. In this work, the...Biaxial strain technology is a promising way to improve the mobility of both electrons and holes, while （100） channel direction appears as to be an effective booster of hole mobility in particular. In this work, the impact of biaxial strain together with （100） channel orientation on hole mobility is explored. The biaxial strain was incorporated by the growth of a relaxed SiGe buffer layer,serving as the template for depositing a Si layer in a state of biaxial tensile strain. The channel orientation was implemented with a 45^o rotated design in the device layout,which changed the channel direction from （110） to （100） on Si （001） surface. The maximum hole mobility is enhanced by 30% due to the change of channel direction from （110） to （100） on the same strained Si （s-Si） p-MOSFETs,in addition to the mobility enhancement of 130% when comparing s-Si pMOS to bulk Si pMOS both along （110） channels. Discussion and analysis are presented about the origin of the mobility enhancement by channel orientation along with biaxial strain in this work.展开更多
Hot carrier effects of p MOSFETs with different oxide thicknesses are studied in low gate voltage range.All electrical parameters follow a power law relationship with stress time,but degradation slope is dependent ...Hot carrier effects of p MOSFETs with different oxide thicknesses are studied in low gate voltage range.All electrical parameters follow a power law relationship with stress time,but degradation slope is dependent on gate voltage.For the devices with thicker oxides,saturated drain current degradation has a close relationship with the product of gate current and electron fluence.For small dimensional devices,saturated drain current degradation has a close relationship with the electron fluence.This degradation model is valid for p MOSFETs with 0 25μm channel length and different gate oxide thicknesses.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61674008,61421005,and 61804003)the National Key Research and Development Program of China(Grant No.2016YFA0202101)the China Postdoctoral Science Foundation(Grant Nos.2018M630034 and 2019T120017)。
文摘The impacts of remote Coulomb scattering(RCS)on hole mobility in ultra-thin body silicon-on-insulator(UTB SOI)p-MOSFETs at cryogenic temperatures are investigated.The physical models including phonon scattering,surface roughness scattering,and remote Coulomb scatterings are considered,and the results are verified by the experimental results at different temperatures for both bulk(from 300 K to 30 K)and UTB SOI(300 K and 25 K)p-MOSFETs.The impacts of the interfacial trap charges at both front and bottom interfaces on the hole mobility are mainly evaluated for the UTB SOI p-MOSFETs at liquid helium temperature(4.2 K).The results reveal that as the temperature decreases,the RCS due to the interfacial trap charges plays an important role in the hole mobility.
文摘The hot carrier effects under off- state stress m ode( Vgs=0 ,Vds<0 ) have been investigated on9nm P- MOSFETs with channel length varying from1.0 2 5 μm to0 .5 2 5 μm.Both on- and off- state currents are discussed. It is found that the off- state leakage current decreases after a higher voltage stressing,which is induced by the charge injection occurred close to the drain junction.However,the leakage current increases after a lower voltage stressing because of the newly generated interface traps.It is also found that the on state saturation current and threshold voltage degrade significantly with the stress tim e,which we believe is due to the charges injected near the gate- drain overlapping region and/ or the stress- induced interface trap generation.The degradation of Idsatcan be ex- pressed as a function of the product of the gate current( Ig) and the num ber of charges injected into the gate oxide ( Qinj) in a simple power law.Finally,a lifetime prediction model based on the degradation of Idsatis proposed.
文摘Biaxial strain technology is a promising way to improve the mobility of both electrons and holes, while （100） channel direction appears as to be an effective booster of hole mobility in particular. In this work, the impact of biaxial strain together with （100） channel orientation on hole mobility is explored. The biaxial strain was incorporated by the growth of a relaxed SiGe buffer layer,serving as the template for depositing a Si layer in a state of biaxial tensile strain. The channel orientation was implemented with a 45^o rotated design in the device layout,which changed the channel direction from （110） to （100） on Si （001） surface. The maximum hole mobility is enhanced by 30% due to the change of channel direction from （110） to （100） on the same strained Si （s-Si） p-MOSFETs,in addition to the mobility enhancement of 130% when comparing s-Si pMOS to bulk Si pMOS both along （110） channels. Discussion and analysis are presented about the origin of the mobility enhancement by channel orientation along with biaxial strain in this work.
文摘Hot carrier effects of p MOSFETs with different oxide thicknesses are studied in low gate voltage range.All electrical parameters follow a power law relationship with stress time,but degradation slope is dependent on gate voltage.For the devices with thicker oxides,saturated drain current degradation has a close relationship with the product of gate current and electron fluence.For small dimensional devices,saturated drain current degradation has a close relationship with the electron fluence.This degradation model is valid for p MOSFETs with 0 25μm channel length and different gate oxide thicknesses.
