To enable efficient sharing of unbounded streaming data,this paper introduces blockchain technology into traditional cloud data,proposing a hybrid on-chain/off-chain storage model.We design a real-time verifiable data...To enable efficient sharing of unbounded streaming data,this paper introduces blockchain technology into traditional cloud data,proposing a hybrid on-chain/off-chain storage model.We design a real-time verifiable data structure that is more suitable for streaming data to achieve efficient real-time verifiability for streaming data.Based on the notch gate hash function and vector commitment,an adaptive notch gate hash tree structure is constructed,and an efficient real-time verifiable data structure for on-chain and off-chain stream data is proposed.The structure binds dynamic root nodes sequentially to ordered leaf nodes in its child nodes.Only the vector commitment of the dynamic root node is stored on the chain,and the complete data structure is stored off-chain.This structure ensures tamperproofing against malicious off-chain cloud servers of off-chain cloud servers.Preserves storage scalability space,realizes the immediate verification of stream data upon arrival,and the computational overhead of on-chain and off-chain hybrid storage verification is only related to the current data volume,which is more practical when dealing with stream data with unpredictable data volume.We formalize this as an efficient real-time verification scheme for stream data in on-chain and off-chain hybrid storage.Finally,the technology’s security and performance were empirically validated through rigorous analysis.展开更多
In this paper, we have investigated the design parameters of RF CMOS switch, which will be used for the wireless tele-communication systems. A double-pole four-throw double-gate radio-frequency complementary-metal-oxi...In this paper, we have investigated the design parameters of RF CMOS switch, which will be used for the wireless tele-communication systems. A double-pole four-throw double-gate radio-frequency complementary-metal-oxide-semicon- ductor (DP4T DG RF CMOS) switch for operating at the 1 GHz is implemented with 45-nm CMOS process technology. This proposed RF switch is capable to select the data streams from the two antennas for both the transmitting and receiving processes. For the development of this DP4T DG RF CMOS switch we have explored the basic concept of the proposed switch circuit elements required for the radio frequency systems such as drain current, threshold voltage, resonant frequency, return loss, transmission loss, VSWR, resistances, capacitances, and switching speed.展开更多
According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barrier...According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.展开更多
Commercially available AlGaN/GaN high-electron-mobility transistors(HEMTs)are beginning to enter the public scene froma range of suppliers.Based on previous studies,commercial GaN-based electronics are expected to be ...Commercially available AlGaN/GaN high-electron-mobility transistors(HEMTs)are beginning to enter the public scene froma range of suppliers.Based on previous studies,commercial GaN-based electronics are expected to be tolerant to different types of irradiation in space.To test this assumption,we compared the characteristic electrical curves obtained at different X-ray irradiation doses for GaN HEMT devices manufactured by Infineon and Transphorm.The p-GaN-based device was found to be more robust with a stable threshold voltage,whereas the threshold voltage of the device with ametal-insulator-semiconductor gatewas found to shift first in the negative and then the positive direction.This dynamic phenomenon is caused by the releasing and trapping effects of radiation-induced charges in the dielectric layer and at the interface of irradiated devices.As such,the p-GaNgate-based GaN HEMT provides a promising solution for use as an electric source in space.展开更多
A program of adaptive quadrature demodulation is proposed to supply the gaps in the traditional analog detection technology of a silicon micro-machined gyroscope (SMG). This program is suitable for digital phase locke...A program of adaptive quadrature demodulation is proposed to supply the gaps in the traditional analog detection technology of a silicon micro-machined gyroscope (SMG). This program is suitable for digital phase locked loop (DPLL) drive technology that proposed in other papers. In addition the program adopts an adaptive filtering algorithm, which selects the in-phase and quadrature components that are outputs of the DPLL of the SMG's drive mode as reference signals to update the amplitude of the in-phase and quadrature components of the input signal by iteratively. An objective of the program is to minimize the mean square error of the accurate amplitudes and the estimated amplitudes of SMG's detection mode. The simulation and test results prove the feasibility of the program that lays the foundation for the further improvement of the SMG's system performance and the implementation of the SMG system's self-calibration and self-demarcation in future.展开更多
Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control tec...Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27℃, supply voltage, VDD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.展开更多
A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many po...A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many power den-sity issues should be reduced by scaling threshold voltage and supply voltage.Initially,Complementary Metal Oxide Semiconductor(CMOS)technology sup-ports power saving up to 32 nm gate length,but further scaling causes short severe channel effects such as threshold voltage swing,mobility degradation,and more leakage power(less than 32)at gate length.Hence,it directly affects the arithmetic logic unit(ALU),which suffers a significant power density of the scaled multi-core architecture.Therefore,it losses reliability features to get overheating and increased temperature.This paper presents a novel power mini-mization technique for active 4-bit ALU operations using Fin Field Effect Tran-sistor(FinFET)at 22 nm technology.Based on this,a diode is directly connected to the load transistor,and it is active only at the saturation region as a function.Thereby,the access transistor can cutoff of the leakage current,and sleep transis-tors control theflow of leakage current corresponding to each instant ALU opera-tion.The combination of transistors(access and sleep)reduces the leakage current from micro to nano-ampere.Further,the power minimization is achieved by con-necting the number of transistors(6T and 10T)of the FinFET structure to ALU with 22 nm technology.For simulation concerns,a Tanner(T-Spice)with 22 nm technology implements the proposed design,which reduces threshold vol-tage swing,supply power,leakage current,gate length delay,etc.As a result,it is quite suitable for the ALU architecture of a high-speed multi-core processor.展开更多
Molecular cloning remains a cornerstone technique in genetic engineering and synthetic biology.In this study,we conducted a systematic comparative analysis between the classical cloning method and the Golden Gate asse...Molecular cloning remains a cornerstone technique in genetic engineering and synthetic biology.In this study,we conducted a systematic comparative analysis between the classical cloning method and the Golden Gate assembly technique,utilizing Escherichia coli as the model organism.Through polymerase chain reaction(PCR)amplification,restriction enzyme digestion,ligation,transformation,and Sanger sequencing,we assessed the operational efficiency and cloning fidelity of both strategies.Our results demonstrated that Golden Gate assembly,leveraging type IIS restriction enzymes and simultaneous ligation,significantly enhanced cloning efficiency and precision,particularly for seamless multi-fragment assembly.In contrast,the classical cloning approach maintained certain advantages in simplicity and robustness for specific experimental conditions.Challenges encountered during transformation and sequencing highlighted the critical impact of technical accuracy on experimental outcomes.This study underscores the importance of selecting appropriate cloning methodologies tailored to experimental objectives and laboratory capabilities,providing a foundation for optimized molecular cloning workflows in future synthetic biology and biotechnology applications.展开更多
增强型氮化镓(GaN)基高电子迁移率晶体管(high electron mobility transistor,HEMT)是高频高功率器件与开关器件领域的研究热点,P-GaN栅技术因具备制备工艺简单、可控且工艺重复性好等优势而成为目前最常用且唯一实现商用的GaN基增强型...增强型氮化镓(GaN)基高电子迁移率晶体管(high electron mobility transistor,HEMT)是高频高功率器件与开关器件领域的研究热点,P-GaN栅技术因具备制备工艺简单、可控且工艺重复性好等优势而成为目前最常用且唯一实现商用的GaN基增强型器件制备方法。首先,概述了当前制约P-GaN栅结构GaN基HEMT器件发展的首要问题,从器件结构与器件制备工艺这2个角度,综述了其性能优化举措方面的最新研究进展。然后,通过对研究进展的分析,总结了当前研究工作面临的挑战以及解决方法。最后,对未来的发展前景、发展方向进行了展望。展开更多
A design of low-light-level night vision system is described,which can image objects selectively in the specific space. The system can selectively image some objects in specific distances,meanwhile ignore those shelte...A design of low-light-level night vision system is described,which can image objects selectively in the specific space. The system can selectively image some objects in specific distances,meanwhile ignore those shelters on the way of observation by combining an intensifying charge coupled device(ICCD) with a near infrared laser assisted in vision,whose operation wavelength matches with the photocathode of the image tube,and adopting the gated mode and adjustable time-delay. A semiconductor laser diode of 100 W in peak power is chosen for illumination. The laser and the image tube operate in 150 ns pulse width and 2 kHz repeat frequency. Some images of different objects at the different distances within 100 m can be obtained clearly,and even behind a grove by using a sampling circuit and a delay control device at 100 W in peak power of semiconductor laser diode,150 ns in pulse width of laser and image tube,2 kHz in repeat frequency.展开更多
基金supported by the National Cryptologic Science Fund of China(Grant No.2025NCSF02020)awarded to Yi Sunsupported by the Natural Science Foundation of Henan Province(Grant No.242300420297)awarded to Yi Sun。
文摘To enable efficient sharing of unbounded streaming data,this paper introduces blockchain technology into traditional cloud data,proposing a hybrid on-chain/off-chain storage model.We design a real-time verifiable data structure that is more suitable for streaming data to achieve efficient real-time verifiability for streaming data.Based on the notch gate hash function and vector commitment,an adaptive notch gate hash tree structure is constructed,and an efficient real-time verifiable data structure for on-chain and off-chain stream data is proposed.The structure binds dynamic root nodes sequentially to ordered leaf nodes in its child nodes.Only the vector commitment of the dynamic root node is stored on the chain,and the complete data structure is stored off-chain.This structure ensures tamperproofing against malicious off-chain cloud servers of off-chain cloud servers.Preserves storage scalability space,realizes the immediate verification of stream data upon arrival,and the computational overhead of on-chain and off-chain hybrid storage verification is only related to the current data volume,which is more practical when dealing with stream data with unpredictable data volume.We formalize this as an efficient real-time verification scheme for stream data in on-chain and off-chain hybrid storage.Finally,the technology’s security and performance were empirically validated through rigorous analysis.
文摘In this paper, we have investigated the design parameters of RF CMOS switch, which will be used for the wireless tele-communication systems. A double-pole four-throw double-gate radio-frequency complementary-metal-oxide-semicon- ductor (DP4T DG RF CMOS) switch for operating at the 1 GHz is implemented with 45-nm CMOS process technology. This proposed RF switch is capable to select the data streams from the two antennas for both the transmitting and receiving processes. For the development of this DP4T DG RF CMOS switch we have explored the basic concept of the proposed switch circuit elements required for the radio frequency systems such as drain current, threshold voltage, resonant frequency, return loss, transmission loss, VSWR, resistances, capacitances, and switching speed.
文摘According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.
基金Thisworkwas supported by the National Key R&D Programof China(No.2017YFB0402800,2017YFB0402802).
文摘Commercially available AlGaN/GaN high-electron-mobility transistors(HEMTs)are beginning to enter the public scene froma range of suppliers.Based on previous studies,commercial GaN-based electronics are expected to be tolerant to different types of irradiation in space.To test this assumption,we compared the characteristic electrical curves obtained at different X-ray irradiation doses for GaN HEMT devices manufactured by Infineon and Transphorm.The p-GaN-based device was found to be more robust with a stable threshold voltage,whereas the threshold voltage of the device with ametal-insulator-semiconductor gatewas found to shift first in the negative and then the positive direction.This dynamic phenomenon is caused by the releasing and trapping effects of radiation-induced charges in the dielectric layer and at the interface of irradiated devices.As such,the p-GaNgate-based GaN HEMT provides a promising solution for use as an electric source in space.
文摘A program of adaptive quadrature demodulation is proposed to supply the gaps in the traditional analog detection technology of a silicon micro-machined gyroscope (SMG). This program is suitable for digital phase locked loop (DPLL) drive technology that proposed in other papers. In addition the program adopts an adaptive filtering algorithm, which selects the in-phase and quadrature components that are outputs of the DPLL of the SMG's drive mode as reference signals to update the amplitude of the in-phase and quadrature components of the input signal by iteratively. An objective of the program is to minimize the mean square error of the accurate amplitudes and the estimated amplitudes of SMG's detection mode. The simulation and test results prove the feasibility of the program that lays the foundation for the further improvement of the SMG's system performance and the implementation of the SMG system's self-calibration and self-demarcation in future.
文摘Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27℃, supply voltage, VDD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.
文摘A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many power den-sity issues should be reduced by scaling threshold voltage and supply voltage.Initially,Complementary Metal Oxide Semiconductor(CMOS)technology sup-ports power saving up to 32 nm gate length,but further scaling causes short severe channel effects such as threshold voltage swing,mobility degradation,and more leakage power(less than 32)at gate length.Hence,it directly affects the arithmetic logic unit(ALU),which suffers a significant power density of the scaled multi-core architecture.Therefore,it losses reliability features to get overheating and increased temperature.This paper presents a novel power mini-mization technique for active 4-bit ALU operations using Fin Field Effect Tran-sistor(FinFET)at 22 nm technology.Based on this,a diode is directly connected to the load transistor,and it is active only at the saturation region as a function.Thereby,the access transistor can cutoff of the leakage current,and sleep transis-tors control theflow of leakage current corresponding to each instant ALU opera-tion.The combination of transistors(access and sleep)reduces the leakage current from micro to nano-ampere.Further,the power minimization is achieved by con-necting the number of transistors(6T and 10T)of the FinFET structure to ALU with 22 nm technology.For simulation concerns,a Tanner(T-Spice)with 22 nm technology implements the proposed design,which reduces threshold vol-tage swing,supply power,leakage current,gate length delay,etc.As a result,it is quite suitable for the ALU architecture of a high-speed multi-core processor.
文摘Molecular cloning remains a cornerstone technique in genetic engineering and synthetic biology.In this study,we conducted a systematic comparative analysis between the classical cloning method and the Golden Gate assembly technique,utilizing Escherichia coli as the model organism.Through polymerase chain reaction(PCR)amplification,restriction enzyme digestion,ligation,transformation,and Sanger sequencing,we assessed the operational efficiency and cloning fidelity of both strategies.Our results demonstrated that Golden Gate assembly,leveraging type IIS restriction enzymes and simultaneous ligation,significantly enhanced cloning efficiency and precision,particularly for seamless multi-fragment assembly.In contrast,the classical cloning approach maintained certain advantages in simplicity and robustness for specific experimental conditions.Challenges encountered during transformation and sequencing highlighted the critical impact of technical accuracy on experimental outcomes.This study underscores the importance of selecting appropriate cloning methodologies tailored to experimental objectives and laboratory capabilities,providing a foundation for optimized molecular cloning workflows in future synthetic biology and biotechnology applications.
文摘增强型氮化镓(GaN)基高电子迁移率晶体管(high electron mobility transistor,HEMT)是高频高功率器件与开关器件领域的研究热点,P-GaN栅技术因具备制备工艺简单、可控且工艺重复性好等优势而成为目前最常用且唯一实现商用的GaN基增强型器件制备方法。首先,概述了当前制约P-GaN栅结构GaN基HEMT器件发展的首要问题,从器件结构与器件制备工艺这2个角度,综述了其性能优化举措方面的最新研究进展。然后,通过对研究进展的分析,总结了当前研究工作面临的挑战以及解决方法。最后,对未来的发展前景、发展方向进行了展望。
文摘A design of low-light-level night vision system is described,which can image objects selectively in the specific space. The system can selectively image some objects in specific distances,meanwhile ignore those shelters on the way of observation by combining an intensifying charge coupled device(ICCD) with a near infrared laser assisted in vision,whose operation wavelength matches with the photocathode of the image tube,and adopting the gated mode and adjustable time-delay. A semiconductor laser diode of 100 W in peak power is chosen for illumination. The laser and the image tube operate in 150 ns pulse width and 2 kHz repeat frequency. Some images of different objects at the different distances within 100 m can be obtained clearly,and even behind a grove by using a sampling circuit and a delay control device at 100 W in peak power of semiconductor laser diode,150 ns in pulse width of laser and image tube,2 kHz in repeat frequency.
