In this paper, a very low-offset continuous time amplifier has been presented. It has the fully differential structure and uses an Auto-zeroed offset stabilization technique. This structure consists of two phases in w...In this paper, a very low-offset continuous time amplifier has been presented. It has the fully differential structure and uses an Auto-zeroed offset stabilization technique. This structure consists of two phases in which the offset value is sampled in the first phase and then subtracted from the signal in the second phase. In order to maintain the continuous time topology, the amplifier uses two paths called main-path and sub-path where the main-path is never disconnected from the signal path and as a result the structure will be continuous time. The amplifier is designed to have a total amount of power dissipation about 3 mW in the standard 0.35 μm CMOS process. Furthermore, the proposed Opamp has an offset value lower than 1 μV at a 2.5 kHz Auto-zeroing frequency, unity gain frequency of 6.14 MHz and phase margin of 78.6° with 50 pF loads.展开更多
This paper presents a low-power high-precision switched-opamp（SO）-based delta-sigma（△Σ） analog-to -digital converter（ADC）.The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to...This paper presents a low-power high-precision switched-opamp（SO）-based delta-sigma（△Σ） analog-to -digital converter（ADC）.The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to work in half of a clock cycle,and thus is suitable for low power applications.In addition,an opamp-sharing technique is applied to save on hardware overheads.Due to the use of a dual cycle shift data weighted averaging （DCS-DWA） technique,mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones.The proposed ADC has been implemented in a standard 0.18μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth.The power consumption is 58μW for the modulator at 0.9 V supply voltage and 96μW for the decimation filter,which translate to the figure-of-merit（FOM） of 35.4 fJ/step for the solo modulator,and 94 fJ/step for the whole system.展开更多
This paper describes a 10-bit,50-MS/s pipelined A/D converter（ADC） with proposed area- and power-efficient architecture.The conventional dedicated sample-hold-amplifier（SHA） is eliminated and the matching requirem...This paper describes a 10-bit,50-MS/s pipelined A/D converter（ADC） with proposed area- and power-efficient architecture.The conventional dedicated sample-hold-amplifier（SHA） is eliminated and the matching requirement between the first multiplying digital-to-analog converter（MDAC） and sub-ADC is also avoided by using the SHA merged with the first MDAC（SMDAC） architecture,which features low power and stabilization.Further reduction of power and area is achieved by sharing an opamp between two successive pipelined stages,in which the effect of opamp offset and crosstalk between stages is decreased.So the 10-bit pipelined ADC is realized using just four opamps. The ADC demonstrates a maximum signal-to-noise distortion ratio and spurious free dynamic range of 52.67 dB and 59.44 dB,respectively,with a Nyquist input at full sampling rate.Constant dynamic performance for input frequencies up to 49.7 MHz,which is the twofold Nyquist rate,is achieved at 50 MS/s.The ADC prototype only occupies an active area of 1.81 mm2 in a 0.35μm CMOS process,and consumes 133 mW when sampling at 50 MHz from a 3.3-V power supply.展开更多
A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk p...A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB （ENOB = 9.69 bits） and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.展开更多
基于CRD对741双极型通用集成运放进行改进研究,通过CRD替代双极型集成运算放大器(OPAMP)输入级及偏置电路中做为恒流源的双极型器件,并利用Multisim 10和Cadence进行设计与仿真。结果表明,当电源电压改变时,双极型运算放大器输入级电流...基于CRD对741双极型通用集成运放进行改进研究,通过CRD替代双极型集成运算放大器(OPAMP)输入级及偏置电路中做为恒流源的双极型器件,并利用Multisim 10和Cadence进行设计与仿真。结果表明,当电源电压改变时,双极型运算放大器输入级电流在0.290 m A到0.433 m A变化,而基于CRD的差分输入级电流恒定在0.239 m A到0.244 m A之间,且电流变化只有0.005 m A。当电源电压恒定在13 V时,双极型运算放大器偏置电流达到0.739 m A,而基于CRD偏置电路电流只有0.222 m。由此可知,基于CRD的运算放大器能实现更低功耗。展开更多
文摘In this paper, a very low-offset continuous time amplifier has been presented. It has the fully differential structure and uses an Auto-zeroed offset stabilization technique. This structure consists of two phases in which the offset value is sampled in the first phase and then subtracted from the signal in the second phase. In order to maintain the continuous time topology, the amplifier uses two paths called main-path and sub-path where the main-path is never disconnected from the signal path and as a result the structure will be continuous time. The amplifier is designed to have a total amount of power dissipation about 3 mW in the standard 0.35 μm CMOS process. Furthermore, the proposed Opamp has an offset value lower than 1 μV at a 2.5 kHz Auto-zeroing frequency, unity gain frequency of 6.14 MHz and phase margin of 78.6° with 50 pF loads.
基金supported by the National Natural Science Foundation of China(No.60906012)
文摘This paper presents a low-power high-precision switched-opamp（SO）-based delta-sigma（△Σ） analog-to -digital converter（ADC）.The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to work in half of a clock cycle,and thus is suitable for low power applications.In addition,an opamp-sharing technique is applied to save on hardware overheads.Due to the use of a dual cycle shift data weighted averaging （DCS-DWA） technique,mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones.The proposed ADC has been implemented in a standard 0.18μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth.The power consumption is 58μW for the modulator at 0.9 V supply voltage and 96μW for the decimation filter,which translate to the figure-of-merit（FOM） of 35.4 fJ/step for the solo modulator,and 94 fJ/step for the whole system.
文摘This paper describes a 10-bit,50-MS/s pipelined A/D converter（ADC） with proposed area- and power-efficient architecture.The conventional dedicated sample-hold-amplifier（SHA） is eliminated and the matching requirement between the first multiplying digital-to-analog converter（MDAC） and sub-ADC is also avoided by using the SHA merged with the first MDAC（SMDAC） architecture,which features low power and stabilization.Further reduction of power and area is achieved by sharing an opamp between two successive pipelined stages,in which the effect of opamp offset and crosstalk between stages is decreased.So the 10-bit pipelined ADC is realized using just four opamps. The ADC demonstrates a maximum signal-to-noise distortion ratio and spurious free dynamic range of 52.67 dB and 59.44 dB,respectively,with a Nyquist input at full sampling rate.Constant dynamic performance for input frequencies up to 49.7 MHz,which is the twofold Nyquist rate,is achieved at 50 MS/s.The ADC prototype only occupies an active area of 1.81 mm2 in a 0.35μm CMOS process,and consumes 133 mW when sampling at 50 MHz from a 3.3-V power supply.
基金Project supported by the National Natural Science Foundation of China(No.60876019)the National S&T Major Project of China(No. 2009ZX0131-002-003-02)+2 种基金the Shanghai Rising-Star Program(No.09QA1400300)the National Scientists and Engineers Service for Enterprise Program,China(No.2009GJC00046)the ASIC State-Key Laboratory Funding,China(No.09MS007)
文摘A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB （ENOB = 9.69 bits） and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.
文摘基于CRD对741双极型通用集成运放进行改进研究,通过CRD替代双极型集成运算放大器(OPAMP)输入级及偏置电路中做为恒流源的双极型器件,并利用Multisim 10和Cadence进行设计与仿真。结果表明,当电源电压改变时,双极型运算放大器输入级电流在0.290 m A到0.433 m A变化,而基于CRD的差分输入级电流恒定在0.239 m A到0.244 m A之间,且电流变化只有0.005 m A。当电源电压恒定在13 V时,双极型运算放大器偏置电流达到0.739 m A,而基于CRD偏置电路电流只有0.222 m。由此可知,基于CRD的运算放大器能实现更低功耗。
